Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-08-22
2006-08-22
Perveen, Rehana (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S107000, C710S112000, C710S039000
Reexamination Certificate
active
07096307
ABSTRACT:
A data processing system has a single configurable write buffer within a peripheral interface unit that is shared among multiple peripherals. Configuration registers are dynamically programmed to control criteria for determining whether control of a system bus will be released prior to completion of a write access to a peripheral. The criteria include which peripheral is being accessed, the particular bus master that is requesting the write request, and a mode of operation, such as supervisor or user write access modes. Write buffering may also be dynamically disabled for individual peripherals based on the state of a peripheral by using a hardware side band signal driven by the peripheral to override a static buffer write policy programmed in control registers.
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Dolezal David G.
Huynh Kim T.
King Robert L.
Perveen Rehana
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