Shared volatile and non-volatile memory

Details Shared volatile and non-volatile memory Shared volatile and non-volatile memory

2002-07-15

2004-09-07

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Parallel read/write

C365S149000, C365S158000, C365S189040

Reexamination Certificate

active

06788605

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to electronic memory. More particularly, the invention relates to shared volatile and non-volatile memory.
BACKGROUND OF THE INVENTION
Electronic memory devices include both volatile and non-volatile memory. Volatile memory is memory that loses its content (data) when power connected to the memory is turned off. Presently, most random access memory (RAM) is volatile. Non-volatile memory is memory that retains its content (data) even when power connected to the memory is turned off. Read only memory (ROM), for example, is generally non-volatile memory.
Dynamic random access memory (DRAM) is a type of volatile memory. DRAM is the most common RAM used in personal computers and workstations. DRAM is dynamic, and unlike static RAM (SRAM), DRAM needs to have its storage cells refreshed or provided with a new electronic charge every few milliseconds. DRAM generally stores each bit in a storage cell consisting of a capacitor and a transistor. Capacitors tend to lose their charge rather quickly, therefore requiring recharging.
FIG. 1
shows a DRAM cell
100
. The DRAM cell
100
includes a charging capacitor CD, and a transistor QD. A logical state, or bit, is stored by the DRAM cell
100
by storing a charge on the charging capacitor CD. The charge on the capacitor CD can be sensed by selecting the DRAM cell
100
through a word line WL, and sensing the voltage across the capacitor CD through a bit line BL. Generally, sensing the voltage across the capacitor CD discharges the capacitor CD, requiring the capacitor CD to be recharged.
Magnetic random access memory (MRAM) is a type of non-volatile memory. MRAM includes storing a logical state, or bit, by setting magnetic field orientations of an MRAM cell. The magnetic field orientations remain even when power to the MRAM cell is turned off.
FIG. 2
shows an MRAM cell
200
. The MRAM memory cell
200
includes a soft magnetic region
220
, a dielectric region
230
and a hard magnetic region
210
. The orientation of magnetization within the soft magnetic region
220
is non-fixed, and can assume two stable orientations as shown by the arrow M
1
. The hard magnetic region
210
(also referred to as a pinned magnetic region) has a fixed magnetic orientation as depicted by the arrow M
2
. The dielectric region
230
generally provides electrical insulation between the soft magnetic region
220
and the hard magnetic region
210
.
As previously stated, the orientation of magnetization of the soft magnetic region
220
can assume two stable orientations. These two orientations, which are either parallel or anti-parallel to the magnetic orientation of the hard magnetic region
210
, determine the logical state of the MRAM memory cell
200
.
The magnetic orientations of the MRAM memory cells are set (written to) by controlling electrical currents flowing through the word lines and the bit lines, and therefore, by the corresponding magnetic fields induced by the electrical currents. Because the word line and the bit line operate in combination to switch the orientation of magnetization of the selected memory cell (that is, to write to the memory cell), the word line and the bit line can be collectively referred to as write lines. Additionally, the write lines can also be used to read the logic value stored in the memory cells.
The orientation of magnetization of the soft magnetic region
220
is determined in response to electrical currents applied to the bit lines (BL) and the word lines (WL) during a write operation to the MRAM memory cell. The electrical currents applied to the bit line and the word line set the orientation of the magnetization of the soft magnetic layer depending upon the directions of the currents flowing through the bit line and the word line, and therefore, the directions of the induced magnetic fields created by the currents flowing through the bit line and the word line.
The MRAM memory cells are read by sensing a resistance across the MRAM memory cells. The resistance is sensed through the word lines and the bit lines.
Reading and writing to MRAM memory cells can take longer than reading and writing to DRAM cells. However, MRAM memory cells offer the advantage of being non-volatile.
Some of the advantages offered by MRAM and DRAM can be realized by physically placing an MRAM integrated circuit that includes an array of MRAM cells proximate to a DRAM integrated circuit that includes an array of DRAM cells. The MRAM, for example, could be used to back up the DRAM. This configuration can be advantageous if a power supply to the DRAM is turned off. This configuration, however, is problematic because physical limitations require the DRAM and MRAM integrated circuits to have a relatively small number of input/output lines. Therefore, backing up an entire array of DRAM cells can be time consuming and complicated because generally the number of input/output lines that access the array of DRAM memory cells is much smaller than the number of memory cells within the array of DRAM memory cells.
It is desirable to have a memory system that includes the benefits of both volatile and non-volatile memory. It is desirable that the memory system should allow for efficient transfer of large amounts of data between the volatile and non-volatile memory.
SUMMARY OF THE INVENTION
The invention includes an apparatus and a method for providing a memory system that includes the benefits of both volatile and non-volatile memory. The memory system allows for efficient transfer of large amounts of data between the volatile and non-volatile memory.
A first embodiment of the invention includes a memory back-up system. The memory back-up system includes a first memory cell, and a non-volatile memory cell that is interfaced to the first memory cell. Control circuitry allows data to be written to either the first memory cell or the non-volatile memory cell, and provides transfer of the data from either the first memory cell or the non-volatile memory cell, to the other of either the first memory cell or the non-volatile memory cell.
Another embodiment of the invention includes memory back-up system. The memory back-up system includes a plurality of first memory cells, and a plurality of non-volatile memory cells that are interfaced to the first memory cells. Control circuitry allows data to be written to either the first memory cells or the non-volatile memory cells, and that provides transfer of the data from either the first memory cells or the non-volatile memory cells, to the other of either the first memory cells or the non-volatile memory cells.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


REFERENCES:
patent: 5250827 (1993-10-01), Inoue et al.
patent: 5640343 (1997-06-01), Gallagher et al.
patent: 6285575 (2001-09-01), Miwa
patent: 6285586 (2001-09-01), Chen et al.
patent: 2001/0023992 (2001-09-01), Doll
patent: 2003/0007411 (2003-01-01), Fukui et al.
patent: 0299633 (1989-01-01), None
Patent Abstracts of Japan vol. 1999, No. 14 Dec. 22, 1999 & JP 11251534A (Fujitsu Ltd) Sep. 17, 1999.

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