Shared translation address caching

Details Shared translation address caching Shared translation address caching

2006-12-05

2006-12-05

Tung, Kee M. (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Cache

C345S542000, C711S113000, C711S118000

Reexamination Certificate

active

07145568

ABSTRACT:
A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data and a cache adapted to store of locations in physical memory available to the graphics subsystem for storing graphics data and available to a graphics controller coupled to the memory controller hub to store graphics data.

REFERENCES:
patent: 5793996 (1998-08-01), Childers et al.
patent: 5914730 (1999-06-01), Santos et al.
patent: 5941968 (1999-08-01), Mergard et al.
patent: 6069638 (2000-05-01), Porterfield
patent: 6097402 (2000-08-01), Case et al.
patent: 6104417 (2000-08-01), Nielsen et al.
patent: 6148357 (2000-11-01), Gulick et al.
patent: 6208273 (2001-03-01), Dye et al.
patent: 6275240 (2001-08-01), Riffault
patent: 6304244 (2001-10-01), Hawkins et al.
patent: 6374317 (2002-04-01), Ajanovic et al.
patent: 6477623 (2002-11-01), Jeddeloh
patent: 6480198 (2002-11-01), Kang
patent: 6480200 (2002-11-01), Fisher
patent: 6496193 (2002-12-01), Surti
patent: 6513099 (2003-01-01), Smith et al.
patent: 6532019 (2003-03-01), Gulick et al.
patent: 6591347 (2003-07-01), Tischler et al.
patent: 6667745 (2003-12-01), Hussain
patent: 6714957 (2004-03-01), Lohman
patent: 6859208 (2005-02-01), White
patent: 0326275 (1989-08-01), None
patent: 0 766 177 (1997-04-01), None
patent: 0 902 355 (1999-03-01), None
patent: 10-247138 (1998-09-01), None
patent: 11-167524 (1999-05-01), None
patent: 1998-54412 (1998-09-01), None
patent: 436694 (2001-05-01), None
patent: WO 99/28893 (1999-06-01), None
patent: WO 99/34293 (1999-07-01), None
patent: WO 00/29934 (2000-05-01), None
patent: WO 02/27499 (2002-04-01), None
VIA Technologies, Inc. Manual, VIA ProSavageTM PM133, http://www.via.com.tw/products/prodpm133.htm; Jan. 19, 2001.
VIA Technologies, Inc. Manual, VIA ProSavageTM PM601, http://www.via.com.tw/products/prodpm601.htm; Jan. 19, 2001.
VIA Technologies, Inc. Manual, VIA APOLLO MVP4, http://www.via.com.tw/products/prodpm601.htm; Jan. 19, 2001.
U.S. Appl. No. 09/595,509 Office Action mailed Jan. 31, 2003.
U.S. Appl. No. 09/595,509 Office Action mailed Jul. 10, 2003.
U.S. Appl. No. 09/644,967 Office Action mailed Jan. 24, 2003.
U.S. Appl. No. 09/644,967 Office Action mailed Jun. 6, 2003.
U.S. Appl. No. 09/644,967 Notice of Allowance mailed Oct. 1, 2003.
English language abstract for Korean Patent Publication, KR 1998-054412, published Sep. 25, 1998, entitled: “A Graphics System Having a Single Memory Structure without Bottleneck”.
Certified English language translation of: Hiroshige GOTO, “Intel in 2000: To investigate the impact of postponement of i820 delivery [Last Half], ” ASCH, Kabushiki Kaisha ASCH, Jan. 1, 2000, dai 24 kan, dai 1 gou, pp. 244-249.
Hiroshige GOTO, “2000 nen no Intel i820 syukka enki no syougeki wo saguru [kouhan], ” title in English: [Intel in 2000: To investigate the impact of postponement of i820 delivery [Last Half]]. ASCH, Kabushiki Kaisha ASCH, Jan. 1, 2000, dai 24 kan, dai 1 gou, pp. 244-249.

Affiliated with

Also associated with

Rating

Shared translation address caching does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shared translation address caching, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shared translation address caching will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3654379