Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2007-06-01
2010-10-12
Kindred, Alford W (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C326S056000, C709S234000, C365S189050, C711S118000
Reexamination Certificate
active
07814243
ABSTRACT:
In one embodiment, payload of multiple threads between intellectual property (IP) cores of an integrated circuit are transferred, by buffering the payload using a number of order queues. Each of the queues is guaranteed access to a minimum number of buffer entries that make up the queue. Each queue is assigned to a respective thread. A number of buffer entries that make up any queue is increased, above the minimum, by borrowing from a shared pool of unused buffer entries on a first-come, first-served basis. In another embodiment, an interconnect implements a content addressable memory (CAM) structure that is shared storage for a number of logical, multi-thread ordered queues that buffer requests and/or responses that are being routed between data processing elements coupled to the interconnect. Other embodiments are also described and claimed.
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Abad Farley J
Kindred Alford W
Rutan & Tucker, LLP.
Sonics, Inc.
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