Shared sense amplifier type semiconductor memory device

Details Shared sense amplifier type semiconductor memory device Shared sense amplifier type semiconductor memory device

1991-11-19

1993-09-07

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Differential sensing

36518907, 365203, 365205, G11C 1140

Patent

active

052435741

ABSTRACT:
A semiconductor memory device with two memory cell arrays. Memory cell arrays are commonly provided with a group of sense amplifiers. Each sense amplifier of a group of sense amplifiers is connected to a corresponding bit line pair within one memory cell array through a transmission transistor pair formed of N channel MOS transistors, and connected to a corresponding bit line pair within the other memory cell array through a transmission transistor pair formed of P channel MOS transistors. The same control signals are applied to gates of these transmission transistor pairs. The control signals maintain 1/2.multidot.Vcc level during a precharge period, and rise to high levels or fall down to low levels.

REFERENCES:
patent: 4858195 (1989-08-01), Soneda
patent: 4943960 (1990-07-01), Komatsu et al.
patent: 4967395 (1990-10-01), Watanabe et al.
patent: 5020031 (1991-05-01), Miyatake
IEEE Journal of Solid-State Circuits, vol. SC-15, No. 5, Oct. 1980, "A 100 ns 5 V Only 64K.times.1 MOS Dynamic RAM", by Chan, et al., pp. 839-846.

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