Shared sense amplifier for ferro-electric memory cell

Details Shared sense amplifier for ferro-electric memory cell Shared sense amplifier for ferro-electric memory cell

2002-04-19

2003-06-03

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S117000, C365S196000, C365S210130

Reexamination Certificate

active

06574135

ABSTRACT:

TECHNICAL FIELD OF INVENTION
The present invention relates generally to the field of memory devices, and more specifically to a Ferro-electric memory device, which provides a means of sharing certain memory circuits and localized access of memory cells in combination with a simple sensing scheme for a sense amplifier used for sensing cells of an FeRAM array in open bit line architecture.
BACKGROUND OF THE INVENTION
Several trends exist presently in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and requiring less power. A reason for these trends is that more personal devices are being fabricated which are relatively small and portable, thereby relying on a small battery as its primary supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device, which has memory and logic functions, integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device which retains its contents while power is not continuously applied thereto is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (“EEPROM”) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory which utilizes a ferroelectric material, such as strontium bismuth tantalate (SBT) or lead zirconate titanate (PZT), as a capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for an FeRAM.
The memory size and memory architecture affects the read and write access times of an FeRAM. Table 1 illustrates exemplary differences between different memory types.
TABLE 1
FeRAM
Property
SRAM
Flash
DRAM
(Demo)
Voltage
>0.5 V
Read > 0.5 V
>1 V
3.3 V
Write (12 V)(±6 V)
Special Transistors
NO
YES
YES
NO
(High Voltage)
(Low Leakage)
Write Time
<10 ns
100 ms
<30 ns
60 ns
Write Endurance
>10
15
<10
5
>10
15
>10
13
Read Time
<10 ns
<30 ns
<30 ns/<2 ns
60 ns
(single/multi bit)
Read Endurance
>10
15
>10
15
>10
15
>10
13
Added Mask for embedded
0
~6-8
~6-8
~3
Cell Size (F ~ metal pitch/2)
~80 F
2
~8 F
2
~8 F
2
~18 F
2
Architecture
NDRO
NDRO
DRO
DRO
Non volatile
NO
YES
NO
YES
Storage
I
Q
Q
P
The non-volatility of an FeRAM is due to the bistable characteristic of the ferroelectric memory cell. An FeRAM cell may be selected by two concurrent X and Y voltage pulses, respectively, wherein X and Y correspond to a specific bit line and word line, respectively, identified by horizontal and vertical decoder circuitry. The FeRAM cells of the capacitor array which receive only one voltage pulse remain unselected while the cell that receives both an X and Y voltage signal flips to its opposite polarization state or remains unchanged, depending upon its initial polarization state, for example.
FIG. 1A
is the characteristic curve plot
10
of a Ferroelectric capacitor. Plot
10
illustrates the charge “Q” (y-axis), and the voltage “V” (x-axis), including the characteristics placement relationship of a “0” state (
15
), and a “1” state (
20
) in a typical FeCap. The voltage “V” (x-axis) ranges from 0 volts (
30
) to V
CC
(
40
). The charge “Q” (y-axis) ranges as high as P+R+S (
50
). The “0” state requires a charge greater than or equal to −(R+P+S), while the “1” state requires a charge greater than or equal to P+R+S to produce a state change of the FeCap.
Also in
FIG. 1A
, the quantity P is the “polarization charge”, R is the “Remnant charge”, and S is the “Saturation charge”. These quantities identify most characteristics of the FeCap. Characteristic curve segment
60
represents the charge path from a “0” state cell, thru V
CC
(
40
) as charge is applied to a FeCap, and then thru curve segment
70
to the stable “1” state as the voltage is relaxed to the FeCap.
FIG. 1B
is the schematic symbol
80
of the Ferroelectric capacitor of
FIG. 1A
, and the typical ½V
CC
polling voltage which is applied to the plate line.
Several types of ferroelectric memory cells are used commonly, a single capacitor memory cell and a dual capacitor memory cell. Further, the single capacitor memory cell is generally broken down into two types; the 1C cell (one capacitor, or capacitor only) and the 1T1C cell (one transistor and one capacitor). The 1C cell has the obvious advantage of requiring one less access/isolation transistor and the accompanying silicon area, but may require more plate lines to limit the capacitance of the lines which couple all the cells wired in common. Because of this capacitance limitation, the 1C cell is seldom used. Both of the single capacitor memory cell types require less silicon area than the dual capacitor type (thereby increasing the potential density of the memory array), but are less immune to noise and process variations. Additionally, the 1C and 1T1C cell requires a voltage reference for determining a stored memory state.
The dual capacitor memory cell (referred to as a 2T2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2T2C memory cell is more stable than a 1T1C memory cell. As illustrated in prior art
FIG. 2
, a 1T1C FeRAM cell
100
includes one transistor
112
and one ferroelectric storage capacitor
114
. A bottom electrode of the storage capacitor
114
is connected to a drain terminal
115
of the transistor
112
. The 1T1C cell
100
is read from by applying a signal to the gate
116
of the transistor (word line WL)(e.g., the Y signal), thereby connecting the bottom electrode of the capacitor
114
to the source of the transistor (the bit line BL)
118
. A pulse signal is then applied to the top electrode contact (the drive line or plate line PL)
120
. The potential on the bitline
118
of the transistor
112
is, therefore, the capacitor charge divided by the bitline capacitance. Since the capacitor charge is dependent upon the bistable polarization state of the ferroelectric material, the bitline potential can have two distinct values. A sense amplifier (not shown) is connected to the bitline
118
and detects the voltage associated with a logic value of either 1 or 0 associated with the FeRAM polarization. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bitline that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of a ferroelectric memory is that a read operation is destructive in some applications. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. If the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite or restore (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. If the drive line voltage was small enough not to switch the ferroelectric then the read operation was not destructive. In general, a non-destructive read requires a much larger capacitor than a destructive read and, therefore, requires a larger cell size.
As illustrated, for example, in prior art
FIG. 3
, a 2T2C memory cell
130
in a memory array couples to a bit line (“bitline”)
132
and an inverse of the bit line (“bitline-bar”)
134
that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The 2T2C ferroelectric memory cell comprises two transistors
136
and
138
and two ferroelectric capacitors

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