Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2002-01-04
2003-02-04
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S207000, C365S189050
Reexamination Certificate
active
06515926
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) memories and devices incorporating dynamic random access memory (“DRAM”) arrays. More particularly, the present invention relates to a shared sense amplifier driver technique for such memories and devices which results in a much improved write recovery time over that of conventional layouts.
Many types of DRAM based devices, or integrated circuits including embedded memory arrays, are currently available including extended data out (“EDO”), synchronous DRAM (“SDRAM”), double data rate (“DDR”) DRAM and the like. Regardless of configuration, the primary purpose of the DRAM is to store data. Functionally, data may be written to the memory, read from it or periodically refreshed to maintain the integrity of the stored data. In current high density designs, each DRAM memory cell comprises a pass transistor coupled to an associated capacitor that may be charged to store a value representative of either a logic level “1” or “0”. Data stored in these memory cells may be read out and written to them through columns of sense amplifiers coupled to complementary bit lines interconnecting rows of these cells.
Certain sense amplifier designs have included cross-coupled complementary metal oxide semiconductor (“CMOS”) latches made up of cross coupled inverters comprising series connected P-channel and N-channel transistors. The common connection of the P-channel devices is generally referred to as the latch P-channel (“LP”) node while the corresponding common connection of the N-channel devices is denominated the latch N-channel (“LN”) node.
Among the possible layouts for columns of such sense amplifiers is to provide a common LP and LN driver device for all of the sense amplifiers. While such an approach may have certain advantages, the LP and LN driver transistors must be very large and the corresponding LP and LN signal lines must be relatively wide. Because of this, relatively slow latching speeds may be experienced resulting in concomitantly slow “read” and “write” speeds. Moreover, data patterns may be encountered which can cause failures such as a logic level “1” in a field of “0s” will tend to latch very late if the number of sense amplifiers in the column is large.
In an attempt to ameliorate certain of these disadvantages, other sense amplifier layouts have incorporated the use of distributed LP and LN drivers in which a relatively smaller pull-up and pull-down transistor is included in each sense amplifier cell instead of much larger devices common to an entire column of sense amplifiers. Through the use of this technique, narrower LPB (latch P-channel bar) and LNB (latch N-channel bar) signal lines may be run vertically to each sense amplifier cell in a column. However, while providing faster “read” speeds than the previously described common LP/LN driver technique (and thinner LPB and LNB signal lines) these designs still exhibit a relatively slow “write” recovery time due to the small size of the single LP driver employed. Moreover, while being somewhat pattern insensitive, these designs also result in a larger on-chip sense amplifier area requirement with individual “read” and “write” column (“Y”) selects and data lines being needed.
SUMMARY OF THE INVENTION
In accordance with the shared sense amplifier driver technique of the present invention, by sharing the selected LP and LN nodes with more than one sense amplifier in a column, yet preserving the distributed local LP/LN driver approach, “write” recovery time can be significantly improved over that of conventional layouts and designs.
Broadly, disclosed herein is an integrated circuit device including an array of memory cells which comprises a plurality of sense amplifiers couplable to the memory cells with each of the sense amplifiers having an associated pull-up and pull-down switching device respectively coupled to a first and second latch node thereof. A first subset of the plurality of sense amplifiers have their first latch node electrically coupled and a second differing number subset of the plurality of sense amplifiers have their second latch node electrically coupled.
Further disclosed herein is an integrated circuit device comprising an array of memory cells wherein the array comprises “N” number of sense amplifiers coupled to bit lines of the array and the memory cells with a first plurality of the N sense amplifiers having a common connected pull-up latch node and a second differing number plurality of the N sense amplifiers having a common connected pull-down latch node.
Particularly disclosed in a representative embodiment of the present invention is a sense amplifier layout wherein the LP node is shared among eight sense amplifiers. Through the use of the technique disclosed herein, the P-channel pull-up device is thereby effectively eight times as strong for a “write” recovery mode where only one Y address is valid so that only one of sixteen (or 1 of 32; or 1 of 1024 etc.) columns is being written.
By also sharing the LN node among groups of two sense amplifiers, the N-channel pull-down device is also stronger for a “write” recovery for the same reason. In this exemplary implementation of the present invention, sharing the LN node with two sense amplifiers is a particularly area efficient approach since adjacent sense amplifiers can share the same active area of a transistor with no area penalty. Experimentally, it has been determined that sharing the LN node with eight sense amplifiers may result in a sense amplifier that is too strong and to which “writes” are then rendered more difficult.
Therefore, for the particular embodiment disclosed herein, it has been determined that sharing the LP node with eight sense amplifiers, and the LN node with two, is optimum for the design and technology of the particular embodiment described. The technique disclosed herein is, nevertheless, applicable to differing technologies, designs and sense amplifier sizes such that other LP and LN node sharing relationships would prove to be optimum, (e.g. 4:1 or 16:4) and the ratio of LP node sharing to LN node sharing can be optimized for a particular design.
Fundamentally, it would desirable to share the maximum number of LN and LP drivers without encountering a pattern sensitivity area. Since N-channel devices are stronger than correspondingly sized P-channel devices (even without ideally simultaneous sensing), the N-channel pull-down transistors effectively do more of the sensing and latching. Since “writes” are effectively a “pull-down” on one data write (“DW”) line (a double high on the DW and complementary data write bar (“DWB”)line is a “write mask”) the P-channel transistors are more important for a “write” restore operation. Consequently, a differing number of shared LN nodes and LP nodes has been found to be optimum.
REFERENCES:
patent: 6154404 (2000-11-01), Hwang
patent: 6249469 (2001-06-01), Hardee
Hardee Kim C.
Parris Michael C.
Hogan & Hartson LLP
Kubida William J.
Lam David
Meza Peter J.
United Memories Inc.
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