Shared peripheral controller

Details Shared peripheral controller Shared peripheral controller

1998-12-17

2001-07-10

Lee, Thomas (Department: 2182)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S029000, C710S036000, C710S052000, C710S059000, C710S107000, C710S120000, C709S241000, C709S241000, C709S248000, C709S241000

Reexamination Certificate

active

06260098

ABSTRACT:

BACKGROUND
1. Field of the Present Invention
The present invention generrlly relates to the field of microprocessor based computers and more particularly to a device and method for sharing a peripheral between processors coupled to the peripheral via two distinct busses.
2. History of Related Art
Microprocessor based computer systems implement various peripheral devices to extend the capability of the system and to reduce the work load placed upon the system's central processing unit. These peripheral devices are coupled to the central processing unit over one or more peripheral busses. These peripheral busses have evolved over time as peripheral devices have become increasingly complex and increasingly fast. The Industry Standard Architecture (ISA) bus was developed in the relatively early stages of microprocessor based computing systems. While the ISA bus had numerous drawbacks that eventually necessitated the development of newer busses, a large number of peripheral devices and adapters designed according to the ISA specification are still prevalent in more modern systems. One of the drawbacks of the ISA bus was its relatively narrow (16bit) I/O address bus. Because only a small number of devices can be uniquely addressed with the ISA address bus, indirect addressing was implemented to expand the capability of ISA devices without altering the specification itself. In an indirect addressing scheme, a device may include multiple internal registers that are individually accessible to the outside world through a single index register, which is given a unique ISA address. The index register is written with a data field indicating which of the internal registers is to be addressed in a subsequent cycle. In the subsequent cycle, a data register, which also has a unique ISA address is read or written to store to or retrieve information from the internal register indicated by the index register.
Prior to the wide spread proliferation of local area networks and network servers, the two cycles required to implement in direct addressing with the ISA bus was an acceptable compromise to maintain compatibility with the enormous base of hardware and software drivers developed around the standard. In many network servers and other sophisticated machines, however, peripheral devices may be accessible from or shared by more than one bus. Sharing of a peripheral device, coupled with the multiple cycle addressing scheme utilized in ISA architectures can lead to improper operation if a processor on one bus is permitted to alter the contents of a shared peripheral's index register while a processor on another bus is attempting to modify or retrieve the contents of the peripheral's data register. Moreover, it is impracticable to address this problem by requiring a software revision to peripheral device drivers for every potentially problematic peripheral device. Accordingly, it is highly desirable to implement a solution for sharing a peripheral device that may require indirect addressing between multiple busses without significantly impacting the performance of the device or system and without requiring revision to existing peripheral device drivers.
SUMMARY OF THE INVENTION
Broadly spealdng the present invention contemplates a shared peripheral controller that includes a primary bus interface, a primary bus first register, a shared bus interface, and a control unit. The primary bus interface is adapted to receive an operation via a primary bus, such as an ISA bus, from a first processor, such as a PCI-to-ISA bus bridge. The shared bus interface is adapted to communicate with a first shared peripheral, such as a real time clock, via a shared bus. The control unit is coupled to the primary bus interface and configured to detect a first segment of a first operation issued by the first processor to the first shared peripheral. The control unit is further configured to buffer the first segment in the primary bus first register until the control unit detects a second segment of the first operation. In response to detecting the second segment, the control unit is configured to issue the first and second segments of the first operation to the first shared peripheral in consecutive cycles of the shared bus.
Preferably the first segment of the first operation includes a data field and an address field where the address field of the first segment is indicative of a primary bus address associated with the first shared peripheral. Preferably, the buffering of the first segment comprises storing the data field in the primary bus first register in response to detecting that the address field matches the primary bus address of the first shared peripheral. In a preferred embodiment, the first shared peripheral includes a plurality of internal register, and the data field of the first segment is indicative of a selected internal register of the first shared peripheral.
In the preferred embodiment, the controller further includes a secondary bus first register and a secondary bus interface that is adapted to receive an operation via a secondary bus, such as a 68000 bus, from a second processor, such as a service processor commonly encountered in a server machine. In this embodiment, the control unit is coupled to the secondary bus interface and configured to detect a first segment of a second operation that is issued by the second processor. The control unit is further adapted to buffer the second operation's first segment in the secondary bus first register until the control unit detects a second segment of the second operation. When the control unit detects the second operation's second segment, the control unit issues the second operation's first and second segments to the first shared peripheral in consecutive cycles of the shared bus.
For embodiments including more than one shared peripheral on the shared bus, the controller may further include a second register set including a primary bus second register and a secondary bus register. In this embodinent, the control unit is configured to detect a first segment of an operation issued by the first processor and destined for the second shared peripheral. The control unit buffers the first segment in the primary bus second register until a second segment of the operation is detected whereupon the controller is configured to issue the first and second segments of the operation to the second shared peripheral in consecutive cycles of the shared bus. Similarly, the control unit detects and buffers a first segment of an operation issued by the second processor for the second shared peripheral in the secondary bus second register until the operation's second segment is detected and then issues the first and second segments to the second shared peripheral in consecutive cycles.
The present invention further contemplates a method of controlling access to a first shared peripheral that is accessible via a primary bus and a secondary bus. A first segment of a first operation issuing from a first processor via the primary bus is detected and buffered in a primary bus first register until a second segment of the first operation is detected. Prior to detecting the second segment, bus activity on the secondary bus may be detected. When the first operation's second segment is ultimately detected, the first and second segments of the first operation are issued to the first shared peripheral device via a shared bus in consecutive cycles of the shared bus. In this manner any activity occurring on the secondary bus between the first and second segments of the first operation is prevented from reaching the shared bus between the first and second segments. In the preferred embodiment, the method further includes detecting a first segment of a second operation issued by a second processor via the secondary bus and buffering the second operation's first segment in a secondary bus first register until a second segment of the second operation is detected. Prior to detecting the second operation's second segment, bus activity on the prim

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