Electrical computers and digital data processing systems: input/ – Access arbitrating – Access prioritizing
Reexamination Certificate
2000-09-13
2003-12-09
Auve, Glenn A. (Department: 2189)
Electrical computers and digital data processing systems: input/
Access arbitrating
Access prioritizing
C710S051000
Reexamination Certificate
active
06662253
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to disk multiprocessing circuits, and, more particularly, to software, systems and methods enabling multiple processors to flexibly share a group of peripheral circuits. Even more particularly, the present invention relates a multiple processor disk drive controller having a shared peripheral architecture.
2. Relevant Background
Multiprocessor architectures have been widely used for general purpose computing systems where it is desired to provide higher instruction throughput. However, multiprocessors have had limited application in embedded computing systems that are less computing intensive. One issue in embedded systems is the efficient sharing of peripherals between the multiple processors in a non-conflicting manner.
Disk drive controller devices are an example of embedded systems that conventionally use a single processor core accessing multiple peripheral circuits. Disk drive controller circuits are circuits that manage data storage and retrieval on associated storage hardware. The disk controller provides a host interface to one or more host computers and conducts data transactions with the host(s) using an available protocol over this host interface. At a basic level, the controller circuit receives read and write requests over the host interface and then performs the requested operation.
A read request typically identifies a location in the storage device from which data is to be read. A response to a read request includes the data stored at the specified location. A write request includes data that is to be written and specifies a location where it is to be stored. In response to a write request the controller causes the data to be stored at the specified location and typically sends an acknowledgment signal to the device that generated the write request.
In addition to these basic transactions a disk controller may support other functionality and interfaces. For example, a controller may include a serial port, a general purpose input output (GPIO) port, RS-232 serial ports and the like. With respect to functionality, the disk drive controller may implement timers, interrupt controllers, diagnostic circuitry, and the like.
Preferably, disk drive controllers are implemented as single integrated circuits having an embedded processor core. The processor core controls one or more peripheral circuits that implemented particular disk drive functionality. The processor core is coupled to the peripherals by a shared peripheral bus. In systems with but a single processor core, there was never a problem with peripheral access as the single processor had complete control over the bus and each peripheral.
The processor executes previously stored program code to implement responses to commands received from host computers. A portion of the code that controls servo functionality (called “servo code”) must operate at a high priority to ensure that the servo mechanism(s) that position the read/write head correctly with respect to the media are performed efficiently and accurately during read and write operations. Other code is also provided to handle lower priority functions such as cache management, defect table management, peripheral interaction, and the like.
There is continuing need to improve the servo control mechanisms. As a result, the servo code is becoming more complex and demands an increasing load on the limited processor resources. At the same time, improvements in disk controller functionality and features result in increasing processor demands being placed by the lower priority code and peripheral circuits. Single processor designs use available interrupt mechanisms to give higher priority to servo code execution when lower priority code competes for processor resources. However, this impacts the ability to execute lower priority code efficiently.
These trends indicate a need for disk drive controllers with greater processing power. In particular, a need exists for disk controllers that implement parallel processing with multiple processing units to handle disk access requests, servo control, and peripheral functionality more efficiently. Multiprocessor designs provide improved ability to prioritize servo code execution while maintaining available processor resource for execution of other code.
To provide improved storage functionality and efficiency, dual processor disk drive controllers are being developed. Dual processors enable the controller to handle multiple tasks in parallel. However, to save chip area it is desirable to implement at least some, if not all, peripheral circuitry as shared between the multiple processor cores. However, this creates contention between the multiple processors whenever both wish to access the same shared peripheral at the same time. Hence, a need exists for software, systems and devices for implementing efficient sharing of peripherals in multi-processor disk controller devices.
SUMMARY OF THE INVENTION
Briefly stated, the present invention involves a disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor selectably couples each of the plurality of processors to the shared bus in response to an owner signal. A set of peripheral-share registers where a first member of the set includes an entry associated with each of the plurality of peripheral units and holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.
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Computer Dictinary, 2ndEdition, 1994, Microsoft Press, pp. 125-126.
Gary Sonya
Tyger Karen
Auve Glenn A.
Jorgenson Lisa K.
Kubida William J.
STMicroelectronics Inc.
Vu Trisha
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