Shared path phase detector having phase indicator

Details Shared path phase detector having phase indicator Shared path phase detector having phase indicator

1998-03-18

2001-04-03

Tse, Young T. (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S374000, C375S376000, C327S157000

Reexamination Certificate

active

06212248

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the design and manufacture of ASIC (application specific integrated circuit) chips and microprocessor chips. More specifically, the present invention relates to the design of the clocking circuit provided internal to the ASIC chip for synchronizing and controlling the sequential operations of the chip.
BACKGROUND OF THE INVENTION
In the design and manufacture of ASIC (application specific integrated circuit) chips and microprocessor chips, it is conventional practice to provide the chip designer with a library of conventional circuits from which to generate the design. Thus, the circuit designs from which the designer must chose are fixed, and also the rules for interconnecting the circuits by wiring are fixed.
Conventionally, one of the circuits used by a chip designer is a phase locked loop (PLL) circuit. PLLs are used to perform two or three different functions. One principal function is to lock or align the output clock of a circuit with the clock input. A second function is to multiply (i.e., increase) or divide (i.e., decrease) the output frequency of a circuit with respect to the input frequency. A third function is to provide clock recovery, i.e., to attenuate the input jitter associated with input signals and recover the clock from jittery data.
The present invention provides improvement over the prior art, which is better understood by first considering the prior art. Referring to
FIG. 1
, a block diagram of a phase locked loop (PLL) circuit according to the prior art is shown. The circuit includes a phase/frequency detector
10
which receives a reference clock input and compares the reference clock input frequency with an output clock signal. The phase/frequency detector
10
also receives as input an output strobe pulse of a feedback divider/pulse generator
12
which provides for frequency multiplication in a well-known manner. The strobe pulse is used within the phase/frequency detector
10
to mask the output clock to accomplish frequency division without delay associated with the feedback divider
12
since the phase/frequency detector is comparing a masked feedback signal directly from the clock output and not from the feedback divider/pulse generator
12
. Generally, the feedback from the clock tree
30
, the feedback divider
12
and the reference clock are used to align the output clock (i.e., clock tree
30
). The phase/frequency detector
10
will output increment (INC) and decrement (DEC) pulses to charge pumps
14
and
16
.
The phase/frequency detector
10
is a rising edge detector. It compares the rising edge of the clock reference signal and rising edge of PLL output clock.
FIG. 2
shows the creation of the INC and DEC outputs of typical prior art phase/frequency detectors. When the output clock phase falls behind or lags the reference clock phase, increment (INC) pulses are generated. The width of this pulse t
1
is equal to the timing difference between the rising edges of the reference clock and output clock. When output clock phase is ahead of or leads the reference clock phase decrement (DEC) pulses are generated. The width of this DEC t
2
pulse equals the timing difference between the rising edges of the output clock and reference clocks. Due to the speed limitations of the phase/frequency detector circuits, no INC or DEC signals will be generated when reference clock and output clock phases align perfectly within a small delta value of each other. When this delta value is around zero, the detector phase crossing is known as “dead zone,” because the detector is functionally “dead” in this region. That is, a “dead zone” is a special case where the phases of the two clock inputs to the phase detector circuit align within a very small delta and cause the two phase detector outputs to go “dead,” meaning that there is not a pulse on either output.
Charge pumps
14
,
16
will generate current pulses equal in width to INC and DEC pulses. INC will add charge to a differential loop filter
18
comprising a pair of capacitors, and DEC will subtract charge from the filter
18
. Charge pump
14
outputs a current signal to filter
18
and either increases or decreases the charge to filter
18
, depending upon whether the signal is to increment or decrement the frequency. The increment/decrement signal is also supplied to the second charge pump
16
which converts the increment/decrement signal to a current output which is fed forward to a differential current controlled oscillator
20
which changes its output frequency in response to change in input current. The use of charge pump
16
which supplies current to the oscillator
20
eliminates the need for a resistor coupled to the capacitor of the filter
18
. In effect, this performs the differentiation function normally accomplished by such a resistor. Thus, if the output clock is earlier in phase than the reference clock, the phase/frequency detector
10
generates a decrement pulse, and the charge pumps
14
,
16
convert this logic signal to current pulses. The pulse from charge pump
14
decreases the voltage across filter
18
. Conversely, if the output clock signal is later in phase than the reference clock, the phase frequency detector
10
generates an increment pulse that the charge pump
14
uses to increase the voltage across the filter
18
. The filter
18
converts the current from the first charge pump
14
to voltage. In essence, the filter
18
and the charge pump
16
smooth the pulses from pulse generator in order to provide smooth DC voltage to current converter
22
.
The output voltage from the filter
18
is supplied as input to the voltage to current converter
22
of conventional design wherein the voltage is converted to current as an output in a well-known manner. The output current from the voltage to current converter
22
is supplied to the differential current controlled oscillator
20
along with the output from the charge pump
16
. These two inputs are summed by the current controlled oscillator
20
to provide a differential output, the frequency of which depends upon the value of the current outputs of voltage to current converter
22
and the second charge pump
16
. The differential voltage output of the differential current controlled oscillator
20
is supplied to CMOS converter
24
of conventional design which converts the differential voltage output of this oscillator
20
to a single ended output of the desired frequency. The output of the CMOS converter
24
is supplied to a forward frequency divider and buffer
26
, of conventional design, which provides a signal having the desired multiple of the input clock frequency as input to a clock distribution tree
30
.
The clock distribution tree
30
is a series of clock circuits designed and utilized by the chip designer to perform various clocking functions that are required. In the case of ASIC chips there may be several chips used each of which requires the same clock timing signals. Since processing variables may tend to introduce different delays from chip to chip in the clock distribution tree, the output from the clock distribution tree rather than the output from forward divider and buffer
26
is used as the input to the phase/frequency detector
10
so as to provide the proper phase alignment in all of the chips running from the same clock irrespective of different delays in different chips. The output from the clock distribution tree is also used as input to feedback divider and buffer
12
, of conventional design, which functions as a frequency multiplier for the output from the phase/frequency detector
10
.
In order to control the frequency multiplication ratio, as well as control the gain of the charge pump
16
, a control circuit
36
is provided which provides signals to a decoder
38
. The decoder
38
provides signals to charge pump
16
and dividers
26
, and
12
to set the frequency multiplication ratios of the circuit in a well known manner. A jitter control circuit
42
is also provided, which will be described in detail presently

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