Shared memory tracing apparatus

Details Shared memory tracing apparatus Shared memory tracing apparatus

2000-08-31

2002-11-19

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S151000, C711S152000, C710S243000, C714S045000

Reexamination Certificate

active

06484243

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a signal processing apparatus in which a large scale integrated circuit (LSI) includes a memory.
BACKGROUND OF THE INVENTION
In prior art signal processing apparatuses, bus information, such as data that appear in a bus accompanying system operation in the event of a trouble of the system and address, is stored using an analyzing apparatus such as a logic analyzer, or a tracing mechanism is incorporated in the system such as described in Japanese Laid-Open Patent Application No. Hei 6-187256.
With recent advances in the semiconductor technologies, LSI's in which various functional blocks and memories have been integrated on a large scale on a single chip have been developed; however, it is impossible to connect an analyzer as no memory interface signal is produced as an output from an LSI chip in the prior art signal processing apparatus configuration, thus suffering a problem of being unable to obtain information necessary for analysis of the operation in the event of a trouble. Also, incorporation of a tracing mechanism inside an LSI will require a control circuit dedicated to trouble analysis and a dedicated trace memory, thus presenting a problem of an increase in the LSI area and cost.
SUMMARY OF THE INVENTION
To address the above problems, the signal processing apparatus of the present invention wherein an LSI includes a memory and a plurality of blocks for accessing the memory comprises a mediation block for mediating the right of using a memory by inputting each memory use request signal produced by a memory access block and makes access to the memory, and a trace control block for producing a memory request signal for storing in the memory access history of the memory based on the result of mediation, and has a quasi mediation function of mediating, during a period in which a memory request signal for writing access history is being approved in the mediation block on the assumption that a memory request signal from other memory access blocks for writing access history has not been approved, and sending back an approval signal. It does not require a control circuit dedicated to trouble analysis or a dedicated trace memory and is capable of preventing an increase in LSI area and cost. The present invention provides a signal processing apparatus in which trouble analysis in the event of a trouble can be easily performed.
First exemplary embodiment of the present invention is a signal processing apparatus in which an LSI has a memory and a plurality of memory access blocks for making access to the memory, which comprises a mediation block for mediating right of use of the memory by inputting each memory use request signal produced by a memory access block, and a trace control block for producing as an output a memory request signal for storing in the memory access history of the memory based on the result of mediation, and which has a quasi mediation function of mediating, during a period in which a memory request signal for writing access history in the mediation block is being approved, assuming that a memory request signal from other memory access block for writing access history has not been approved and sending back an approval signal. It has a function in which a trace control block traces memory access history in the memory based on the result of mediation by the mediation block.


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Australian Patent Office Search Report dated Apr. 5, 2001.
Australian Patent Office Examination Report dated Apr. 5, 2001.

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