Shared memory system

Details Shared memory system Shared memory system

1996-08-26

1999-09-28

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711150, 711151, 711211, 3642292, 3649314, G06F 1516

Patent

active

059604581

ABSTRACT:
A parallel processing system in which access contention of a read cycle from a processing unit side to a local shared memory and a write cycle from a shared bus system side on the local shared memory is reduced and a memory LSI which may be used in such unit are provided. The parallel processing system comprises the local shared memory between the processor and a shared bus. Address and data input means (WA and DI) for writing data to a memory cell and address input means (RA) and data output means (DO) for reading data are provided independently from each other to parallelize operations for reading from the processor side and for writing from the shared bus side.

REFERENCES:
patent: 4153934 (1979-05-01), Sato
patent: 4270167 (1981-05-01), Koehler et al.
patent: 4833649 (1989-05-01), Greub
patent: 5025365 (1991-06-01), Mathur et al.
patent: 5079694 (1992-01-01), Nakagawa et al.
patent: 5146607 (1992-09-01), Sood et al.
patent: 5388230 (1995-02-01), Yamada et al.
patent: 5576997 (1996-11-01), Masuda et al.

Affiliated with

Also associated with

Rating

Shared memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shared memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shared memory system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-716338