Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2005-08-18
2010-10-12
Shah, Sanjiv (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S148000, C711S149000, C710S029000, C710S030000, C710S052000, C710S317000, C370S358000, C370S359000, C370S360000
Reexamination Certificate
active
07814280
ABSTRACT:
A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is operable to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of the data segments in the shared memory. The scheduling circuitry is further operable to facilitate striping of each data segment of a frame across the memory banks in one of the rows, and to facilitate striping of successive data segments of the frame across successive rows in the array.
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Cummings Uri
Lines Andrew
Pelletier Patrick
Southworth Robert
Fulcrum Microsystems Inc.
Savla Arpan P.
Shah Sanjiv
Weaver Austin Villeneuve and Sampson LLP
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