Shared memory multiprocessor performing cache coherency

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

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711141, 711147, 711149, 711169, G06F 1314

Patent

active

060887702

ABSTRACT:
A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is "0", a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers. The command of access to the shared area is multicast to all of the nodes, whereas the command is multicast only to the nodes within the corresponding partition when the local area is accessed.

REFERENCES:
patent: 4985825 (1991-01-01), Webb, Jr. et al.
patent: 5710907 (1998-01-01), Hagersten et al.
patent: 5890189 (1999-03-01), Nozue et al.
patent: 5956754 (1999-09-01), Kimmel
"DDM-A Cache-Only Memory Architecture", Computer, Sep. 1992, vol. 25, issue 9, pp. 44-54.
"Cache coherent shared memory hypercube", Parallel and Distributed Processing, 1992. Proceedings of the 4th IEEE Symposium, Dec. 1-4 1992, pp. 515-520.
"Software Cachingon cache-coherent multiprocessors", Parallel and Distributed Processing, 1992. Proceedings of the 4th IEEE Symposium, Dec. 1-4 1992, pp. 521-526.
"Evolved System Architecture", Sun World, Jan. 1996, pp. 29-32.
"The Stanford Flash Multiprocessor", (The 21st Annual International Symposium on Computer Architecture, Apr. 18-21, 1994, Chicago, Illinois, pp. 302-313.
"Hive: Fault Containment for Shared-Memory Multiprocessors" (15th ACM Symposium on Operating Systems Principles, Dec. 3-6, 1995, Copper Mountain Resort, Colorado, pp. 12-25.

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