Shared memory multiprocessor memory model verification...

Details Shared memory multiprocessor memory model verification... Shared memory multiprocessor memory model verification...

2005-05-10

2005-05-10

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S141000, C712S030000

Reexamination Certificate

active

06892286

ABSTRACT:
A system and method for verifying a memory consistency model for a shared memory multiprocessor computer systems generates random instructions to run on the processors, saves the results of the running of the instructions, and analyzes the results to detect a memory subsystem error if the results fall outside of the space of possible outcomes consistent with the memory consistency model. A precedence relationship of the results is determined by uniquely identifying results of a store location with each result distinct to allow association of a read result value to the instruction that created the read result value. A precedence graph with static, direct and derived edges identifies errors when a cycle is detected that indicates results that are inconsistent with memory consistency model rules.

REFERENCES:
patent: 5692153 (1997-11-01), Malik et al.
patent: 20020166032 (2002-11-01), Qadeer

Affiliated with

Also associated with

Rating

Shared memory multiprocessor memory model verification... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shared memory multiprocessor memory model verification..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shared memory multiprocessor memory model verification... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3383740