Shared memory interface in a programmable logic device using...

Details Shared memory interface in a programmable logic device using... Shared memory interface in a programmable logic device using...

2005-09-20

2009-06-09

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07546572

ABSTRACT:
Partial reconfiguration of a programmable logic device is used in combination with a shared memory block for communicating between two blocks of an electronic circuit design. In one embodiment, a shared memory is implemented on RAM resources of a field programmable gate array (FPGA), and a first design block implemented in resources of the FPGA is coupled to the shared memory. A second design block is also coupled to the shared memory. In response to a write request by the second design block, a process determines the RAM resources of the FPGA that correspond to the shared memory address in the write request. A configuration bitstream is generated to include configuration data for partial reconfiguration of the FPGA with the data from the write request at the appropriate RAM resources. The FPGA is partially reconfigured with the configuration bitstream via a configuration port of the FPGA.

REFERENCES:
patent: 2005/0193359 (2005-09-01), Gupta et al.
patent: 2006/0015674 (2006-01-01), Murotake
Mignolet, J.-Y.; Nollet, V.; Coene, P.; Verkest, D.; Vernalde, S.; Lauwereins, R. Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip. Design, Automation and Test in Europe Conference and Exhibition, 2003, pp. 986-991.
Xilinx, Inc.; XAPP138; “Virtex FPGA Series Configuration and Readback”; (v2.8), Mar. 11, 2005; available from Xilinx, Inc., 2100 Logic drive, San Jose, California 95124; pp. 1-37.
Xilinx, Inc.; XAPP139; “Configuration and Readback of Virtex FPGAs Using (JTAG) Boundary Scan”; (v1.6), Sep. 12, 2003; available from Xilinx, Inc., 2100 Logic drive, San Jose, California 95124; pp. 1-17.
Xilinx, Inc.; XAPP290; “Two Flows for Partial Reconfiguration: Module Based or Difference Based”; (v1.2), Sep. 9, 2004; available from Xilinx, Inc., 2100 Logic drive, San Jose, California 95124; pp. 1-28.

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