Shared memory controller having an address error detector

Details Shared memory controller having an address error detector Shared memory controller having an address error detector

1998-03-18

2000-07-25

Yoo, Do Hyun

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

711110, 711217, 711218, 711219, 711221, 370392, H02H 305

Patent

active

060947322

ABSTRACT:
A shared memory controller prevents a memory area in a shared memory from becoming unusable even if an error occurs in an address for performing read/write operations. Under the control of a write control unit, each time N units of data and an address indicative of a storage location next to this data is written into the shared memory, one of the written addresses is stored in a second memory provided separately from the shared memory. Each time N addresses are read from the shared memory, an address stored in the second memory is read to detect in a detector whether or not the address is erroneous. If an error is detected, the erroneous address is discarded.

REFERENCES:
patent: 4320466 (1982-03-01), Myers
patent: 5513318 (1996-04-01), Goor et al.
patent: 5530806 (1996-06-01), Condon et al.
patent: 5586253 (1996-12-01), Green et al.
patent: 5742600 (1998-04-01), Nishihara
patent: 5790782 (1998-08-01), Martinez et al.
patent: 5870394 (1999-02-01), Oprea
patent: 5893162 (1999-04-01), Lau et al.

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