Shared memory control system and shared memory control method

Details Shared memory control system and shared memory control method Shared memory control system and shared memory control method

1998-07-22

2002-09-24

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S150000, C711S151000, C711S158000, C710S240000, C710S244000, C710S241000

Reexamination Certificate

active

06457106

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a shared memory control system and a shared memory control method, for systematically controlling a plurality of bus masters accessing only one shared memory.
2. Description of Related Art
FIG. 8
is a block diagram illustrating a schematic construction of a prior art shared memory system. In this drawing, Reference Numerals
301
and
302
designate bus masters BM
1
and BM
2
, accessing a shared memory. These bus masters and a shared memory
304
are connected by a data bus
310
. Reference Numeral
303
indicates an arbiter for executing a shared memory bus arbitration.
When the bus masters BM
1
and BM
2
access the shared memory
304
, the bus masters BM
1
and BM
2
dispatch a shared memory access authority request signal (access request signals
311
and
313
), to inform the arbiter
303
of the shared memory access request.
The arbiter
303
executes the shared memory bus arbitration. Namely, if the access request is dispatched from the bus master BM
1
or BM
2
by the shared memory access request signal
311
or
313
, the arbiter
303
gives an access enable signal
312
or
314
to either of the bus masters.
Now, assuming that the bus master BM
1
obtains the shared memory access authority, an address command signal
307
is supplied from the bus master BM
1
through a buffer
305
and a shared memory bus
309
of the shared memory
304
, with the result that the memory access is performed. Similarly, when the bus master BM
2
obtains the shared memory access authority, an address command signal
308
is supplied through a buffer
306
and the shared memory bus
308
of the shared memory
304
, with the result that the memory access is performed.
A basic example of arbitration under the shared memory access control, mentioned above, is rotating arbitration. In a simple rotating arbitration, after the arbiter
303
gives the shared memory access authority to a bus master once, even if another bus master newly requests the shared memory access, it is necessary to maintain the bus master newly requesting the shared memory access in a waiting condition until the bus master currently holding the shared memory access authority abandons the access authority. This presents a problem.
In order to avoid this problem, the arbiter must forcibly deprive the shared memory access authority from the bus master which has the authority. Thus, the arbiter and a function circuit become disadvantageously complicated. Therefore, in order to avoid this disadvantage, for example, Japanese Patent Application Laid-open Publication No. JP-A-03-137754 discloses an access control method for determining the bus master allowed to access the shared memory at each cycle of the shared memory access. However, this method does not have a means for ensuring a memory access band width per a constant time, required for each of a plurality of bus masters accessing the shared memory.
On the other hand, another prior art shared memory control system shown in
FIG. 9
, an address command signal given to a shared memory
405
is centrally controlled by a shared memory controller
404
, and bus masters BM
1
(
401
) and BM
2
(
402
) using the shared memory do not directly control the address command given to the shared memory
405
.
In conclusion, in the prior art shared memory control methods shown in
FIGS. 8 and 9
, when the bus master BM
1
or BM
2
obtains right to exclusively use the bus
310
or
417
, a maximum exclusively occupying time of the bus is individually set for each of the bus masters BM
1
and BM
2
and for each bus occupying occasion. Therefore the shared memory access time is restricted so as to elevate the utilization factor of the bus
310
or
417
.
Now, when there are a plurality of bus masters executing a read/write access to only one shared memory, if a bus master accessing the shared memory is replaced by another, a page address supplied to the shared memory is often changed, with the result that a page missing occurs, and a read/write processing is temporarily interrupted. This presents a problem.
In other words, the prior art shared memory control systems have a problem that it does not pay attention to an arbitration for ensuring the memory access band width per unit time, required by each bus master of a plurality of bus masters accessing the shared memory.
SUMMARY OF THE INVENTION
In view of the above mentioned circumstance, it is an object of the present invention to provide a shared memory control system and a shared memory control method, capable of realizing a memory control having an excellent efficiency by maintaining the memory access band width per unit time, required by the master.
In order to achieve the above mentioned object of the present invention, according to a first aspect of the present invention there is provided a shared memory control method wherein in a current shared memory cycle, a memory access band width of each bus master is calculated at any time, and before completion of the current shared memory cycle, a next memory cycle control is determined so as to maintain the minimum memory access band width required by each bus master.
In addition, according to a second aspect of the present invention there is provided a shared memory control apparatus including a shared memory, and a shared memory controller for controlling a plurality of bus masters accessing the shared memory, the apparatus including a calculating means for calculating, for each of the plurality of bus masters, a memory access band value &phgr; required per a unit time to the shared memory and a shared memory access band value &psgr; at a time in a current shared memory cycle, and a prediction and control means for comparing the memory access band value &phgr; with the shared memory access band value &psgr; to perform, before completion of the current shared memory cycle, a prediction processing for maintaining the shared memory access band value &psgr;.
Furthermore, according to a third aspect of the present invention there is provided a shared memory control apparatus including, a plurality of bus masters accessing only one shared memory, the apparatus including a means for comparing, for each of the bus masters, a first shared memory access band value required per a unit time, with a second shared memory access band value of each bus master calculated at any time in a current shared memory cycle, to perform a prediction processing for maintaining the first shared memory access band value at a predetermined value.
In the present invention, in the current shared memory cycle, the memory access band width value of each bus master is calculated at any time and discriminated to determine the next memory cycle control before completion of the current shared memory cycle. Thus, the minimum memory access band width value required by each bus master is maintained with the result that the shared memory can be efficiently utilized.


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