Shared memory array for data block and control program storage i

Details Shared memory array for data block and control program storage i Shared memory array for data block and control program storage i

1993-04-30

1995-11-07

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 364DIG2, 3642362, 364239, 3642394, 364243, 3642434, 36424341, 36424342, 3642455, 3642456, 364246, 3642481, 395827, 395894, 395496, G06F 1312

Patent

active

054653436

ABSTRACT:
An improved disk drive architecture includes a microcontroller interface circuit connected between a drive microcontroller and a buffer controller. The microcontroller interface circuit includes address mapping registers for mapping at least one predetermined portion of directly addressable memory of the microcontroller to address locations of the drive's cache buffer. The buffer controller circuit includes an access arbitration circuit for arbitrating requests for access to the cache buffer by the drive's data sequencer, the drive's host interface controller and the drive's microcontroller. A microcontroller wait state generator responds to the access arbitration circuit by generating and applying a wait state sequence to the microcontroller until a request it makes for access to the cache buffer can be executed.

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patent: 5072420 (1991-12-01), Conley et al.
patent: 5084791 (1992-01-01), Thanos et al.
Excerpt, CL-SH350 Integrated Synchronous SCSI Disk Controller, Prelim. Data Sheet, Cirrus Logic, Inc, Milpitas, Calif. Nov. 1988, pp. 1-3, 21-23, 59-66.
OTI-018, Oak Technology, Inc., Hard Disk Controller Chip Engineering Specification Jun. 1992, Version 4.00.

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