Shared memory array

Details Shared memory array Shared memory array

2001-09-14

2004-08-24

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S170000, C711S147000, C711S153000, C710S022000, C710S027000, C710S028000, C710S306000, C712S010000, C712S020000, C712S235000

Reexamination Certificate

active

06782463

ABSTRACT:

BACKGROUND
1. Field
Disclosure provided herein relates to processing circuitry. In particular, embodiments provided herein relate to the use of memory arrays.
2. Information
Embedded processing architectures typically comprise a core processing circuitry coupled to a data bus. Such an embedded processing architecture is typically formed in a semiconductor die as a “system-on-a-chip” with interfaces to external data bus elements or memory devices in a processing platform. The external data bus elements or memory devices typically provide data and instructions to be executed by the core processing circuit.
An embedded processing system typically comprises a local memory to provide data storage and retrieval with low latencies. Such local memory may be a shared memory which is accessible through an internal data bus. Core processing circuitry may also be associated with one or more levels of cache memory which the core processing circuitry may access independently of the internal data bus.


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Intel 80303 I/O Processor Developer's Manual, Jun. 2000, Chapters 1-4.

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