Shared memory architecture in GPS signal processing

Details Shared memory architecture in GPS signal processing Shared memory architecture in GPS signal processing

2005-07-18

2011-11-29

Nguyen, Thu (Department: 2452)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S153000, C701S120000

Reexamination Certificate

active

08069314

ABSTRACT:
A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

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