Shared memory architecture

Details Shared memory architecture Shared memory architecture

2011-05-10

2011-05-10

Farrokh, Hashem (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C709S224000

Reexamination Certificate

active

07941613

ABSTRACT:
Disclosed herein is an apparatus which may comprise a plurality of nodes. In one example embodiment, each of the plurality of nodes may include one or more central processing units (CPUs), a random access memory device, and a parallel link input/output port. The random access memory device may include a local memory address space and a global memory address space. The local memory address space may be accessible to the one or more CPUs of the node that comprises the random access memory device. The global memory address space may be accessible to CPUs of all the nodes. The parallel link input/output port may be configured to send data frames to, and receive data frames from, the global memory address space comprised by the random access memory device(s) of the other nodes.

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