Shared memory-access priorization method for multiprocessors usi

Details Shared memory-access priorization method for multiprocessors usi Shared memory-access priorization method for multiprocessors usi

1997-04-14

1999-08-17

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711158, 711144, 711118, G06F 1200

Patent

active

059408642

ABSTRACT:
A method of reducing memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. When a requesting processing unit issues a message indicating that it desires to read a value from an address of a memory device of the computer system, each cache snoops an interconnect to detect the message, and transmits a response to the message, wherein a shared intervention response is transmitted to indicate that a cache containing an unmodified value corresponding to the address of the memory device can source the value. A priority is associated with each response, and system logic detects each response and its associated priority, and forwards a response with a highest priority to the requesting processing unit. The protocol may include prior-art coherency responses such as an invalid response, a modified intervention response, a shared response, and a retry response. Either the retry response or the shared intervention response may be assigned a highest priority. Since the cache latency can be much less than the memory latency, the read performance can be substantially improved with this new protocol.

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