Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-02-25
2001-09-04
Dharia, Rupal (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S240000, C710S241000, C710S244000, C710S107000, C710S112000, C710S114000, C710S115000, C710S116000, C710S117000, C710S118000
Reexamination Certificate
active
06286070
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a bus controller, and, more particularly, to a bus controller for arbitrating access requests of a plurality of microcontrollers to a shared memory.
A bus controller is provided between a plurality of microcontrollers and a memory. The bus controller arbitrates access requests from respective microcontrollers to the shared memory and generally sequentially provides access authority to the microcontroller having a highest priority. The bus controller provides a bus wait signal to the microcontrollers having a lower priority. The microcontrollers having the lower priority wait until the processing operation of the microcontroller having the higher priority terminates, at which time the bus controller again determines which microcontroller will be granted access to the memory.
FIG. 1
is a schematic block diagram of a conventional bus controller. A memory controller (bus controller)
50
is connected to first and second microcontrollers
51
and
52
via CPU buses
53
and
54
. Each of the microcontrollers
51
and
52
supplies an access signal such as a read instruction or a write instruction to the memory controller
50
. Now, assume the first microcontroller
51
has a higher priority than the second microcontroller
52
. When the access requests are made from the first and second microcontrollers
51
and
52
to the memory controller
50
, the memory controller
50
controls a memory
55
in accordance with the access request from the first microcontroller
51
. For example, the memory controller
50
reads data from the memory
55
in accordance with a read access request of the first microcontroller
51
and temporarily stores the data in a data buffer
50
a
and then supplies the stored data to the first microcontroller
51
via the CPU bus
53
. The memory controller
50
further lowers a bus wait signal RDY supplied to the second microcontroller
52
from an H level (high potential or logical value “1”) to an L level (low potential or logical value “0”). The second microcontroller
52
waits in response to the bus wait signal RDY low.
FIG. 2
is a timing chart explaining the operation of the memory controller
50
and the second microcontroller
52
. The memory controller
50
receives a read signal RD low for a read operation supplied from the second microcontroller
52
and in return, supplies the bus wait signal RDY low to the second microcontroller
52
. The second microcontroller
52
supplies the read instruction to the memory controller
50
and waits.
When the transfer of the data read from the memory
55
to the first microcontroller
51
has terminated, the memory controller
50
then controls the memory
55
in accordance with the read instruction from the second microcontroller
52
. At this time, the memory controller
50
raises the bus wait signal RDY from an L level to an H level. The second microcontroller
52
resets the wait state in response to the bus wait signal RDY high and receives read data from the data buffer
50
a
. The second microcontroller
52
cannot receive read data from the data buffer
50
a
while it is waiting. As a result, the efficiency of the second microcontroller
52
is reduced. In particular, when an access request is made from another microcontroller having a higher priority than the second microcontroller
52
while the second microcontroller
52
is waiting, the wait time of the second microcontroller
52
is prolonged, such that it may enter a bus locked state.
It is an object of the present invention to provide a bus controller that improves the processing efficiency of microcontrollers.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided that arbitrate access requests to a shared memory from a plurality of controllers including a first controller and a second controller having a lower access priority than the first controller. First, an operation mode of the second controller is set in one of a wait mode and a non-wait mode. Then, the access enabling of the first controller and the access disabling of the second controller are decided in accordance with access priority when the access requests from the first and second controllers compete with each other. Then, a first signal for resetting a wait state for the first controller is supplied a second signal for resetting a wait state for the second controller is supplied when the second controller is set in the non-wait mode.
In another aspect of the present invention, a bus controller is provided that arbitrate access requests to a shared memory from a plurality of controllers including a first controller and a second controller having a lower access priority than the first controller. The bus controller includes a first register for storing one of wait mode data and non-wait mode data set for the second controller. An arbitration circuit is connected to the first and second controllers, receives access requests from the first and second controllers, decides the access enabling of the first controller, and decides the access disabling of the second controller when the access requests from the first and second controllers compete with each other. A first bus access controller is connected to the arbitration circuit and supplies a first signal for resetting the wait state of the first controller in accordance with the decision of the access enabling of the first controller. A second bus access controller is connected to the first register and the arbitration circuit and supplies a second signal for resetting the wait state of the second controller when the access disabling of the second controller is determined and the non-wait mode data is stored in the first register.
In yet another aspect of the invention, an electronic device is provided that includes a plurality of controllers including first and second controllers and a memory shared by the plurality of controllers. The second controller has a lower access priority than the first controller. A bus controller is connected between the plurality of controllers and the memory and arbitrate access requests to the shared memory from the plurality of controllers. The bus controller includes a first register for storing one of wait mode data and non-wait mode data set for the second controller. An arbitration circuit is connected to the plurality of controllers for receiving access requests from the first and second controllers and decides the access enabling of the first controller and access disabling of the second controller when the access requests from the first and second controllers compete with each other. A first bus access controller is connected to the arbitration circuit and supplies a first signal for resetting a wait state of the first controller in accordance with the decision of the access enabling of the first controller. A second bus access controller is connected to the first register and the arbitration circuit and supplies a second signal for resetting the wait state of the second controller when the access disabling to the second controller is determined and the non-wait mode data is stored in the first register.
REFERENCES:
patent: 4987529 (1991-01-01), Craft et al.
patent: 5191656 (1993-03-01), Forde, III et al.
patent: 5784582 (1998-07-01), Hughes
patent: 4-148453 (1992-05-01), None
Dharia Rupal
Fujitsu Limited
Staas & Halsey , LLP
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