Shared I/O ports for multi-core designs

Details Shared I/O ports for multi-core designs Shared I/O ports for multi-core designs

1999-08-26

2002-12-17

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C710S036000, C710S064000, C709S208000

Reexamination Certificate

active

06496880

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to input/output (I/O) ports. More particularly, it relates to the efficient use of I/O ports with multi-core integrated circuit designs.
2. Background of Related Art
Many processors (e.g., microprocessors, microcontrollers, digital signal processors (DSPs)) communicate with external or peripheral devices using general purpose input/output (I/O) ports. While address and data buses are also typically provided by processors, I/O ports allow flexibility in designs to accommodate signals not necessarily comporting to the strict timing requirements of an address and data bus communication. For instance, I/O ports are ideal for writing and/or reading single bit data (rather than byte or word-length data) to or from a particular device.
An I/O port typically includes a plurality of I/O pins, e.g., eight (8) I/O pins. Each I/O pin is typically configurable as either an input or an output. The configuration of each I/O pin typically takes place during an initialization of the relevant core, and may be reconfigured during operation of the relevant core.
FIG. 3
shows the relevant portions of a conventional arrangement of I/O ports and pins with respect to a plurality of cores (e.g., processors) on a common integrated circuit or hybrid circuit.
In particular, a plurality of cores
600
-
604
are arranged on an integrated circuit or on a hybrid circuit
650
. Each of the cores
600
-
604
has its own purpose or function, and is provided individual access external to the circuit
650
by pins protruding from a hermetically sealing package formed around the circuit
650
. Each core
600
-
604
typically includes a respective I/O port
620
-
624
, and each respective I/O port
620
-
624
has an associated number of I/O pins
630
-
634
.
In today's world of integrated circuit design, a significant restriction that designers have had to cope with is the limited number of external pins available for use in any particular package design. The external pins are generally soldered or socketed onto a printed circuit board (PCB).
Generally, as the required number of external pins increases, the size of the package design must increase accordingly to accommodate the larger number of external pins. Ideally, designers would like to have an unlimited number of external pins available for interfacing a given integrated circuit or hybrid circuit device with the external world (e.g., a PCB). Unfortunately, design trends are toward reduced size of components, allowing devices having reduced size.
As technology advances, the need has arisen for multiple cores within the same integrated circuit or hybrid circuit. However, the ability to keep external pin count to a minimum in light of the additional cores (e.g., processors) within an integrated circuit becomes quite strained.
In response to the need for multiple cores within a given integrated circuit or hybrid circuit, designers have been forced to rely on expensive packaging solutions, such as high density pin grid arrays with, e.g., hundreds of external pins to be bonded out, to accommodate the large number of external interfaces to be made with respect to each core.
There is a need for a more efficient design allowing multiple cores within an integrated circuit or hybrid circuit to communicate with the external world exhibiting reduced pin count.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a multi-core circuit device comprises a first core and a second core. A configurable interconnect includes a communication path to the first core and to the second core. A shared I/O port allows use of at least one shared I/O pin by one of the first core and the second core based on a configuration established by the configurable interconnect.
A method of sharing at least one I/O pin between a plurality of cores in a multi-core circuit device in accordance with another aspect of the present invention comprises configuring the at least one shared I/O pin from a first one of the plurality of cores in the multi-core device for use by another one of the plurality of cores in the multi-core circuit device, upon initiation of operation of the multi-core circuit device.


REFERENCES:
patent: 5668419 (1997-09-01), Oktay
patent: 5907485 (1999-05-01), Van Loo et al.
patent: 6182206 (2001-01-01), Baxter
patent: 6266797 (2001-07-01), Godfrey et al.
patent: 6285211 (2001-09-01), Sample et al.

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