Shared floating-point unit in a single chip multiprocessor

Details Shared floating-point unit in a single chip multiprocessor Shared floating-point unit in a single chip multiprocessor

1997-05-15

2000-11-14

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

712220, 712221, 712 23, G06F 900

Patent

active

061483958

ABSTRACT:
A single-chip multiprocessor (2, 102) is disclosed. The multiprocessor (2, 102) includes multiple central processing units, or CPUs, (10, 110) that share a floating-point unit (5, 105). The floating-point unit (5, 105) may receive floating-point instruction codes from either or both of the multiple CPUs (10, 110) in the multiprocessor (2, 102), and includes circuitry (52) for decoding the floating-point instructions for execution by its execution circuitry (65). A dispatch unit (56) in the floating-point unit (5, 105) performs arbitration between floating-point instructions if more than one of the CPUs (10, 110) is forwarding instructions to the floating-point unit (5, 105) at the same time. Dedicated register banks, preferably in the form of stacks (60), are provided in the floating-point unit (5, 105). The disclosed multiprocessor (2, 102) provides efficiency in allowing sharing of the floating-point unit (5, 105) by the multiple CPUs (10, 110), considering that the utilization of a floating-point unit (5,105) by a single CPU (10, 110) is generally relatively low.

REFERENCES:
patent: 5598546 (1997-01-01), Blomgren
patent: 5673407 (1997-09-01), Poland et al.
patent: 5732209 (1998-03-01), Vigil et al.
patent: 5828578 (1998-10-01), Blomgren

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