Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-02-04
2003-12-09
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S773000
Reexamination Certificate
active
06662333
ABSTRACT:
TECHNICAL FIELD
The technical field is error correcting code for semiconductor memory.
BACKGROUND
Semiconductor memories are subject to errors that may affect operation of connected systems. A typical error may result when a particular memory location is exposed to one or more a particles. Such radiation may cause a data bit stored in the memory location to flip from a “1” to a “0.”
Error correcting codes (ECC) are used to enhance reliability and state integrity of computer semiconductor memory subsystems. Error correcting codes are known that will correct a single error, and will detect, but not correct, a double error. Other ECCs will detect and correct multiple errors. For ECC applications, memory array chips may be organized so that errors generated in a chip can be corrected by the ECC.
Correction of single bit errors and detection of double bit errors may be accomplished by use of check bits. A typical ECC implementation appends a number of check bits to each data word. The appended check bits are used by ECC logic circuits to detect errors within the data word. The simplest and most common form of error control is implemented through the use of parity bits. A single parity bit is appended to a data word and assigned to be a 0 or a 1, so as to make the number of 1's in the data word even in the case of even parity codes, or odd in the case of odd parity codes.
Prior to transmission of the data word in a computer system, the value of the parity bit is computed at the source point of the data word and is appended to the data word. On receipt of the transmitted data word, logic at the destination point recalculates the parity bit and compares it to the received, previously appended parity bit. If the recalculated and received parity bits are not equal, a bit error has been detected. Use of parity codes has the disadvantage, however, of not being able to correct bit errors and cannot detect even bit errors. For example, if a data bit changes from a 0 to a 1 and another data bit changes from a 1 to a 0 (a double bit error), the parity of the data word will not change and the error will be undetected.
By appending additional parity bits to the data word, each corresponding to a subset of data bits within the data word, the parity bit concept may be extended to provide detection of multiple bit errors, or to determine the location of single or multiple bit errors. Once a data bit error has been detected, logic circuits may be used to correct the erroneous bit, providing single error correction.
A well known error correction code is the Hamming code, which appends a series of check bits to the data word as it is stored in memory. Upon a read operation, the retrieved check bits are compared to recalculated check bits to detect and to locate (i.e., correct) a single bit error. By adding more check bits and appropriately overlapping the subsets of data bits represented by the check bits, other error correcting codes may provide for multiple error corrections and detection. While current computer systems often incorporate single error correction and multiple error detection, the parity check bits required by the error code occupy space in the semiconductor memory. This space is not available for memory operations.
SUMMARY
A method for detecting and correcting errors in a semiconductor memory includes partitioning the memory into M memory blocks, each of the M memory blocks capable of containing k data bits. The k data bits include a plurality of error correcting code (ECC) bits generated by a common ECC block. The method further includes assigning r ECC bits to the M memory blocks and distributing the r ECC bits among the M memory blocks. The value of r is determined using the product M×k and the type of ECC code used. The M memory blocks share the common ECC block for ECC bits generation and for error detection and correction.
A shared ECC circuit operating with a semiconductor memory having a plurality of memory units includes a plurality of ECC cells corresponding to the plurality of memory units. Each of the plurality of memory units is capable of containing a plurality of data bits. The shared ECC circuit further includes a common ECC block that generates ECC bits. The ECC bits are included in the plurality of data bits, and a number of ECC bits in the plurality of ECC cells relates to a total number of data bits stored in the plurality of memory units. In addition, the ECC bits are distributed among the plurality of memory units, and the plurality of memory units share the common ECC block for ECC bits generation and for error detection and correction.
Hardware to implement ECC check bits using current systems is illustrated in FIG.
1
. An error correcting code circuit
10
includes a memory line
11
, which is shown in
FIG. 1
including 30 data bits. Associated with the memory line
11
is an ECC cell
12
that stores a single data value with one or more data bits. Referring to Table 1 above, seven ECC bits are required to be stored in the ECC cell
12
to accomplish single bit error correction and double bit error detection in the memory line
11
. An ECC block
13
is used to generate the ECC bits and to perform the error correcting/detecting code operations including checking the data bits in the memory line
11
during read and write operations.
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Johnson Jenny R. C.
Zhang Kevin
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