Shared embedded microcontroller interface

Details Shared embedded microcontroller interface Shared embedded microcontroller interface

1997-03-14

2002-09-03

Myers, Paul R. (Department: 2181)

Electrical computers and digital data processing systems: input/

Interrupt processing

Reexamination Certificate

active

06446153

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention pertains to a shared embedded microcontroller interface, and more particularly, to an interface with an embedded controller that is shared between a system management environment and an operating system environment.
Embedded controllers are used extensively in mobile computer designs, and are becoming increasingly more prevalent in desktop and server designs, as well. Embedded controllers were initially used as standard Personal Computer (PC) architecture keyboard controllers. Eventually, these keyboard controllers were modified to add numerous features for use with the System Management Mode (SMM) of the microprocessors designed and manufactured by Intel Corporation, Santa Clara, Calif. A description of the operation of System Management Mode software for power management can be found at pages 1-228 to 1-289 of the publication “Peripheral Components,” 1996 by Intel Corporation, the disclosure of which is hereby incorporated by reference in its entirety. Referring to
FIG. 1
, a computer system
10
is shown which includes such a microcontroller. A central processing unit (CPU)
11
is provided, such as a Pentium® microprocessor from Intel Corporation, Santa Clara, Calif. The CPU
11
is coupled to a first bridge circuit
13
(also referred to as a host bridge or north bridge), which in turn is coupled to a bus
15
, such as a bus operated according to the Peripheral Component Interconnect (PCI) architecture (Version 2.1, 1995, PCI Special Interest Group, Portland, Oreg.). The first bridge circuit
13
is also coupled to memory
14
. Coupled to the PCI bus
15
is a second bridge circuit
17
(also called a south bridge), which in turn can be coupled to an extension bus
19
. An embedded controller
21
of the type mentioned above can be coupled to the extension bus
19
. An enhanced version of this embedded controller
21
may include a family of parts and a high performance CPU core with upwards of one hundred general purpose input-output pins.
The embedded controller
21
includes a host interface. Often, this host interface is one byte wide and allows real-time communication with the CPU
11
. Typically, two address ranges are decoded at the host interface: 60H/64H (hexadecimal) for standard keyboard functionality and 62H/66H for system management activities. Embedded controllers in mobile environments are typically coupled to a plurality of system devices (e.g., battery
22
a
and IDE power plane switch
22
b
) and are responsible for a large amount of monitoring and control activities including, but not limited to function key System Management Interrupt (SMI) generation, thermal management, battery management, switch management, power plane control, suspend sequencing, etc. In these systems, communication between the CPU
11
and the controller
21
may occur through the use of an interrupt (e.g., an SMI). In the system shown in
FIG. 1
, the controller
21
places data in an addressable register and then asserts an interrupt to the CPU
11
. The interrupt is handled by the execution of system management code that can be stored in the memory
14
. Accordingly, in response to the interrupt, the CPU
11
suspends its current processing and responds to the interrupt to handle the appropriate operation based on the value placed in the addressable register by the controller
21
.
As an example, the embedded controller
21
can be used to monitor a battery
22
a
which supplies power to the computer system
10
. If the battery supply is nearing depletion, that condition is sensed by the embedded controller
21
which places the appropriate byte in its output register and alerts the CPU
11
by asserting the System Management Interrupt. In response, the CPU
11
suspends its current processing and executes system management code. During the execution of the SM code, the output register of the embedded controller is read by the CPU
11
and appropriate actions are taken (e.g., alert the user by displaying a message indicating battery supply depletion). The CPU
11
can also execute system management code to control a system device coupled to the embedded controller
21
, such as an IDE power plane switch
22
b.
During execution of system management code, the CPU
11
writes a command to an input register of the embedded controller
21
. In response to the command, the embedded controller
21
controls the operation of the IDE power plane switch
22
b
(e.g., disconnects a device from the IDE power plane in order to reduce power consumption).
If the execution of operating system code in the CPU
11
or other processing unit were to take over some of the aforementioned communication with the embedded controller
21
to obtain important power management information (battery, power plane control, thermal control, suspend switches, etc.) and to receive important power management events when they occur (e.g., low battery warning, A.C. adapter insertion, etc.), the embedded controller
21
will not also be able to efficiently communicate with the SM handler (i.e., the CPU
11
executing system management code in the example of
FIG. 1
) to process special events such as the depression of functions keys at the keyboard. Accordingly, there is a need for a method and apparatus to allow for an embedded controller to interface with what could be a multi-tasking, multi-processing operating system as well as being shared by the execution of system management code.
SUMMARY OF THE INVENTION
The present invention provides an embedded controller that can interface with both an operating system and a system management code. According to an embodiment of the present invention, a computer system is provided having a central processing unit (or two or more processing units) adapted to execute operating system code stored in a first memory area and system management code stored in a second memory area. An embedded controller having a host interface is coupled to the central processing unit via the host interface and first and second interrupts. The first interrupt is used by the central processing unit during the execution of the operating system code and the second interrupt is used by the central processing unit during the execution of the system management code. The embedded controller is additionally coupled to at least one system device in the computer system and the central processing unit communicates with the embedded controller via the host interface and the first and second interrupts while executing the operating system code and the system management code. Accordingly, the central processing unit is capable of monitoring and/or controlling the system device via communication with the embedded controller.


REFERENCES:
patent: 5903894 (1999-05-01), Reneris
patent: 5937200 (1999-08-01), Frid et al.
Advanced Configuration and Power Interface Specification Revision 1.0 Dec. 22, 1996.

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