Shared data lines for memory write and memory test operations

Details Shared data lines for memory write and memory test operations Shared data lines for memory write and memory test operations

1998-03-19

1999-08-10

Mai, Son

Static information storage and retrieval

Read/write circuit

Testing

36518907, G11C 700

Patent

active

059369019

ABSTRACT:
The present invention is embodied in a method and apparatus which permits the testing of a memory device by utilizing normally unused data write lines to conduct the results of the memory test operations to a memory controller or processor. The data read from a specific memory cell is input into a comparator through a data sense amplifier and compared to the data from another memory cell. When the data is not coincident, a switch is enabled causing a data write line to change states. The change of state of the data write line disables a buffer, causing it to output a tri-state signal. A controller detects and interprets the tri-state signal output from the buffer as improper memory functioning.

REFERENCES:
patent: 5400342 (1995-03-01), Matsumura et al.
patent: 5436911 (1995-07-01), Mori
patent: 5457696 (1995-10-01), Mori
patent: 5548596 (1996-08-01), Tobita
patent: 5646948 (1997-07-01), Kobayashi et al.
patent: 5673270 (1997-09-01), Tsujimoto
patent: 5684809 (1997-11-01), Stave et al.
patent: 5689514 (1997-11-01), Saitoh

Affiliated with

Also associated with

Rating

Shared data lines for memory write and memory test operations does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shared data lines for memory write and memory test operations, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shared data lines for memory write and memory test operations will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1126545