Shared contact in a semiconductor device in which DRAMs and...

Details Shared contact in a semiconductor device in which DRAMs and... Shared contact in a semiconductor device in which DRAMs and...

2002-06-05

2004-02-10

Nguyen, Cuong Q. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S393000, C257S903000

Reexamination Certificate

active

06690053

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device in which DRAMs and SRAMs are combined. It particularly relates to a semiconductor device having a structure in which a shared contact that is effective for reducing a cell area of SRAMs can be easily formed, and to a method of manufacturing the device.
2. Description of the Prior Art
FIG. 9
is a circuit diagram showing the memory cell of a SRAM used in a conventional semiconductor device. Referring to
FIG. 9
, PMOS load transistors
101
and
102
each serve as a load, NMOS drive transistors
103
and
104
each serve as a charge puller, NMOS access transistors
105
and
106
each serve as an information deriver to a bit line, Vcc is a power supply line, GND is a grand line, and WL is a word line. In addition, NMOS access transistor
105
connects with bit line ‘BL’, and NMOS access transistor
106
connects with bit bar line ‘/BL’.
FIG. 10
is a layout diagram showing the memory cell of a SRAM used in a conventional semiconductor device, and it is a layout sample of the circuit diagram shown in FIG.
9
. In
FIG. 10
, because the same or corresponding part is designated by the same numeral as the one in
FIG. 9
, the explanation is omitted. Gate
111
is the gate of PMOS load transistor
101
and NMOS drive transistor
103
, gate
112
is the gate of PMOS load transistor
102
and NMOS drive transistor
104
, gate
113
is the gate of NMOS access transistor
105
, and gate
114
is the gate of NMOS access transistor
106
.
Additionally, in
FIG. 10
, on-the-active-region contact
115
is the on-the-active-region contact of NMOS drive transistor
103
and NMOS access transistor
105
, on-the-gate contact
116
is the on-the-gate contact of PMOS load transistor
102
and NMOS drive transistor
104
, on-the-active-region contact
117
is the on-the-active-region contact of PMOS load transistor
101
, on-the-active-region contact
118
is the on-the-active-region contact of PMOS load transistor
102
, on-the-gate contact
119
is the on-the-gate contact of PMOS load transistor
101
and NMOS drive transistor
103
, on-the-active-region contact
120
is the on-the-active-region contact of NMOS drive transistor
104
and NMOS access transistor
106
, first layer aluminum wiring
121
connects on-the-active-region contacts
115
,
117
, and on-the-gate contact
116
, first layer aluminum wiring
122
connects on-the-active-region contacts
118
,
120
and on-the-gate contact
119
, first layer aluminum wiring
123
connects with PMOS load transistor
101
, on-the-active-region contact
124
is the on-the-active-region contact of PMOS load transistor
102
, and first layer aluminum wiring
125
connects with on-the-active-region contact
124
.
Additionally, first layer aluminum wiring
121
is the cross coupling part that connects the output of PMOS load transistor
101
and NMOS drive transistor
103
to gate
112
of PMOS load transistor
102
and NMOS drive transistor
104
, and first layer aluminum wiring
122
is the cross coupling part that connects the output of PMOS load transistor
102
and NMOS drive transistor
104
to gate
111
of PMOS load transistor
101
and NMOS drive transistor
103
. Through-holes and aluminum wirings existing above the first layer aluminum wiring are not shown. In the layout sample shown in
FIG. 10
, contacts
115
-
120
, and
124
are independently arranged. Herein, contacts
115
-
120
, and
124
independently arranged are occasionally referred to as “usual contact”.
FIG. 11
is a layout diagram showing the memory cell of a SRAM used in the conventional semiconductor device, and it is a sample of the reduction of the cell region by use of a shared contact in comparison to the layout diagram shown in FIG.
10
. Because in
FIG. 11
the same numerals show the same or equivalent parts to the ones in
FIG. 10
, the explanation is omitted. Shared contact
131
forms on-the-gate contact
116
and on-the-active-region contact
117
by use of one contact, and shared contact
132
forms on-the-gate contact
119
and on-the-active-region contact
118
by use of a simple contact. As shown in
FIG. 11
, because the cell size in the direction of the gate width is reduced, the cell region of the SRAM can be reduced.
FIG. 12
is a sectional view showing the manufacturing process of a SRAM in the conventional semiconductor device, and it corresponds to the sectional view along the line A-A′ shown in FIG.
11
. In
FIG. 12
, well
201
is present within the silicon substrate; isolation oxide film
202
and gate oxide film
203
are formed on well
201
; gate electrode
204
is equivalent to gate
112
; gate wiring
205
is equivalent to the wiring part of gate
111
; side wall
206
is formed over the sidewall of gate electrode
204
; side wall
207
is formed over the sidewall of gate electrode
205
; diffused layer
208
is the diffused layer of source/drain; silicide layer
209
is a silicide layer over diffused layer
208
; silicide layer
210
is a silicide layer over gate electrode
204
; silicide layer
211
is a silicide layer over gate wiring
205
; and silicon nitride film
212
is formed over isolation oxide film
202
.
Moreover, in
FIG. 12
, contact interlayer film
213
is formed with silicon dioxide film; barrier metals
214
and
215
each are formed over the bottom and the sidewall of the contact; tungsten plugs
216
and
217
(referred to as W plug hereinafter) each are formed within the contact holes; barrier metals
218
and
219
are respectively formed over the bottom of aluminum wirings
220
and
221
; and ARC (Anti Reflective Coat) films
222
and
223
are formed as an anti-reflecting film in a photolithography process. Here, on-the-active-region contact
124
corresponds to the area where barrier metal
214
and W plug
216
are formed; shared contact
132
corresponds to the area where barrier metal
215
and W plug
217
are formed; first layer aluminum wiring
122
corresponds to the area where barrier metal
218
, aluminum wiring
220
, and ARC film
222
are formed; and first layer aluminum wiring
125
corresponds to the area where barrier metal
219
, aluminum wiring
221
, and A RC film
223
are formed. On-the-active-region contact
124
and shared contact
132
are formed in the same process, and they are not formed in different processes, for instance, a photolithography process and an etching process. Incidentally, although not shown in the sectional view, contacts existing on gates
113
and
114
are also formed in the same process as the process in which on-the-active-region contact
124
and shared contact
132
are formed.
Examples of the patent disclosing the conventional semiconductor device described above include Japanese Patent No. 3,064,999 and U.S. Pat. No. 6,031,271.
The conventional semiconductor device has been constructed as mentioned above. As a result, because in a system LSI in which DRAMs and SRAMs are combined, a contact interlayer film is thicker in order to form the capacitor layer of the DRAM, there exist a drawback that forming a usual or typical contact and a shared contact at the same time is difficult; the failure of junction leakage occurs; and the contact resistance increases.
The drawback of the conventional technology will next be described in detail.
In the process of manufacturing the SRAM of the conventional semiconductor device shown in
FIG. 12
, since the film thickness of contact interlayer film
213
is 0.5-0.8 &mgr;m, on-the-active-region contact
124
and shared contact
132
can be formed at the same time. On the other hand, in the manufacturing process of a system LSI in which DRAMs and SRAMs are combined, because the film thickness of contact interlayer film
213
should be 1.0-3.0 &mgr;m in order to form the capacitor layer of the DRAM, the simultaneous formation of on-the-active-region contact
124
and shared contact
132
becomes difficult.
Additionally, in
FIG. 12
, when on-the-active-region contact
124
and shared contact
132
are formed by etching con

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