Shared cache line update mechanism

Details Shared cache line update mechanism Shared cache line update mechanism

2005-01-04

2005-01-04

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S138000, C711S141000

Reexamination Certificate

active

06839816

ABSTRACT:
Embodiments are provided in which cache updating is described for a computer system having at least a first processor and a second processor having a first cache and a second cache, respectively. When the second processor obtains from the first processor a lock to a shared memory region, the first cache pushes to the second cache cache lines for the addresses in the shared memory region accessed by the first processor while the first processor had the lock.

REFERENCES:
patent: 5566319 (1996-10-01), Lenz
patent: 5611058 (1997-03-01), Moore et al.
patent: 5895484 (1999-04-01), Arimilli et al.
patent: 5940856 (1999-08-01), Arimilli et al.
patent: 6108757 (2000-08-01), Arshad
patent: 6167489 (2000-12-01), Bauman et al.
patent: 6477620 (2002-11-01), Bauman et al.

Affiliated with

Also associated with

Rating

Shared cache line update mechanism does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shared cache line update mechanism, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shared cache line update mechanism will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3375606