Shared bypass bus structure

Details Shared bypass bus structure Shared bypass bus structure

2005-06-28

2005-06-28

Vo, Tim (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S317000, C370S225000, C370S447000, C711S138000, C711S141000

Reexamination Certificate

active

06912612

ABSTRACT:
A shared bypass bus structure for low-latency coherency controller access in a coherent scalable switch. In a coherent scalable switch with multiple coherent interconnect ports, distributed coherency control structures, and a crossbar interface between them, a shared bypass bus permits data transfer between the coherent interconnect ports and the coherency control structures while bypassing the crossbar interface. Some embodiments may comprise scalable switches to support one or more sets of processors with substantially independent snoop or cache coherency paths or arrangements.

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High Bandwidth, Low Latency Interconnection Network for Information Transfer, IBM Techinical Disclosure Bullentin, Jan. 1996.

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