Shared bit line memory device and method

Details Shared bit line memory device and method Shared bit line memory device and method

2006-08-15

2006-08-15

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S063000, C365S230030, C365S230050

Reexamination Certificate

active

07092279

ABSTRACT:
A memory array employing shared bit-lines. A memory is formed from an array of plural bit-cells organized as plural columns and plural rows. Plural word-lines are aligned with each for the rows, and each is electrically coupled to a discrete fraction of the bit-cells its corresponding row. The memory also includes plural bit-lines that are aligned with the plural columns. Every bit-line is electrically coupled to all of the bit-cells that lie along at least one column. In addition, at least a first one of the bit-lines is further electrically coupled to all of the bit-cells in an additional column. That bit-line is coupled such that every one of the plural bit-cells, that lie along any given row that are coupled to it, is coupled to a unique word-line from the other bit-cells coupled thereto. The shared bit-line invention is applicable to single and multiple port memory arrays. It is applicable to all memory array technologies including, but not limited to, SRAMs and DRAMs.

REFERENCES:
patent: 5276650 (1994-01-01), Kubota
patent: 6243285 (2001-06-01), Kurth et al.
patent: 6707708 (2004-03-01), Alvandpour et al.
patent: 6711051 (2004-03-01), Poplevine et al.
patent: 6711067 (2004-03-01), Kablanian
patent: 6741492 (2004-05-01), Nii
patent: 6781867 (2004-08-01), Kurth et al.

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