Shallow trench isolation with conductive hard mask for...

Details Shallow trench isolation with conductive hard mask for... Shallow trench isolation with conductive hard mask for...

1999-12-02

2001-03-20

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

Reexamination Certificate

active

06204073

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of test structures for semiconductor processing and more specifically to test structures for in-line electrical measurement of moat/trench width during semiconductor processing.
BACKGROUND OF THE INVENTION
Shallow trench isolation (STI) is being widely used for isolation in large-scale integrated circuits (ICs) to isolate the active areas of transistors and other devices from each other. STI is formed prior to transistor formation. Typically, a pad oxide and pad nitride are deposited over the surface. The pad oxide and nitride are then patterned and etched to form a hard mask for the trench etch. A shallow trench is then etched into the semiconductor surface. A trench liner is then formed on the surface of the trench and the trench is filled with a dielectric material, such as silicon dioxide. This is followed by CMP and removal of nitride to create active areas.
As ICs become denser, both the active areas and the trench shrink. This places increasing demands on the lithography used to pattern the hard mask/trench. It also requires tighter control of the trench etch. The STI lithography and etch can be monitored/evaluated using top-view SEM (scanning-electron-microscope)/cross-sectional SEM. Since large amounts of data are required for wafer uniformity, SEM analysis becomes time-consuming. Accordingly, a method for monitoring/developing/evaluating STI lithography and etch that is less time consuming and provides wafer uniformity information is desired.
SUMMARY OF THE INVENTION
A method for forming STI that allows for in-situ moat/trench width electrical measurement is disclosed herein. A conductive layer is used in either the hard mask or as part of the resist layer for trench etch. After the mask is formed, the resistance of the conductive layer is measured over a predefined length. Since the length is known, the average width of the mask/moat can be determined. Once the width of the moat is known, the width of the trench can easily be determined by subtracting the width of the moat from the pitch, which is a known factor. The conductive layer is removed either during the resist strip or during etch prior to CMP.
An advantage of the invention is providing a structure for in-line measurement of moat/trench width using electrical resistance.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.


REFERENCES:
patent: 5365102 (1994-11-01), Mehrotra et al.
patent: 5637898 (1997-06-01), Baliga

Affiliated with

Also associated with

Rating

Shallow trench isolation with conductive hard mask for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shallow trench isolation with conductive hard mask for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shallow trench isolation with conductive hard mask for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2497154