Shallow trench isolation type semiconductor device and...

Details Shallow trench isolation type semiconductor device and... Shallow trench isolation type semiconductor device and...

2001-07-31

2002-12-31

Thomas, Tom (Department: 2811)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S296000, C438S437000, C257S311000, C257S374000

Reexamination Certificate

active

06500726

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a shallow trench isolation (STI) type semiconductor device and method of forming the same. More particularly, the present invention relates to a STI type semiconductor device and method of forming the same, which can prevent the electric field from concentrating to an edge portion of a substrate in an active region.
2. Description of the Related Art
As the elements incorporated into a semiconductor device are integrated to a high degree, there is a growing tendency to increasingly use an STI method as a method of forming an isolation layer as compared with a local oxidation of silicon (LOCOS) method.
The STI method generally comprises etching a substrate to form trenches for isolation, and filling the trenches with an insulating layer. Thus, each of isolated regions is separated by the trenches and the insulating layer filled therein. However, when the trenches are filled with an oxide layer for insulation and a subsequent thermal process is carried out, the oxygen diffusion sometimes occurs at interfaces or edges of the oxide layer to oxidize corresponding portions of the inner walls of the trenches additionally. At this time, since the volume is increased due to the oxidation, damage such as a dislocation of crystallized structure may occur.
To solve this problem, there is proposed a method of using a silicon nitride liner. An example of that method is disclosed in U.S. Pat. No. 5,747,866 to Ho et al., in which, after the silicon nitride liner is formed on an inner wall of a trench, the trench is filled with a silicon oxide layer. At this time, the silicon nitride liner acts as an oxygen diffusion stop layer to prevent the damage of the substrate due to the oxidation. However, in this case, another problem may be presented, as described below.
FIG. 1
to
FIG. 4
illustrate flow diagrams of the process steps of a conventional method of forming an STI type semiconductor device, demonstrating a problem when a silicon nitride liner is formed in an inner wall of a trench.
Referring to
FIG. 1
, first a pad oxide film
11
is formed on a substrate
10
. Then, a silicon nitride layer as an etch protecting layer
13
is deposited on the pad oxide film
11
. Thereafter, the etch protecting layer
13
in a trench-intended region is removed by means of a patterning process. The patterning process is carried out through a general photolithography and etching. Continuously, the substrate
10
is etched to form a trench
15
by using the etch protecting layer
13
as a mask.
Referring to
FIG. 2
, an inner wall oxide film
17
is formed to a thickness of 200 to 300 Å in an inner wall of the trench
15
by means of a thermal oxidation process. The thermal oxidation process cures damages generated on the inner wall of the trench
15
during the etching process for forming the trench
15
. Then, a silicon nitride layer is formed over the whole surface of the substrate
10
. Consequently, a liner
19
is formed in the inner wall of the trench
15
.
Referring to
FIG. 3
, a CVD silicon oxide layer
21
is deposited over the substrate
10
over which the liner
19
is formed. As a result, the trench
15
is filled with the CVD silicon oxide layer
21
. Then, the portion of the CVD silicon oxide layer
21
formed on the etch protecting layer
13
in an active region is removed by planarization etching.
Referring to
FIG. 4
, the etch protecting layer
13
covering the active region is wet-etched and removed. At this time, a top end of the liner
19
coming in contact with the etch protecting layer
13
is also removed. Particularly, since the etch protecting layer
13
is over-etched to be completely removed, the top end of the liner
19
is deeply etched below the upper surface of the substrate
10
. Consequently, a reduced liner
19
′ only remains between the isolation layer and the active region, so that a ‘dent’ phenomenon of forming a concave space in the place in which the removed top end of the liner
19
was located occurs. This concave space is enlarged in the following cleaning process, when the CVD silicon oxide layer
21
and the inner wall oxide film
17
adjacent thereto are etched by means of a fluoride containing detergent.
When the ‘dent’ phenomenon occurs, the concave space may be filled with polysilicon in the following process for forming gates. Polysilicon filled in the concave space may result in a gate bridge. Also, it may cause a ‘hump’ phenomenon of forming parasite transistors, which makes normal transistor elements not form the linear transistor characteristic, and increases of the leakage current.
To prevent the ‘dent’ phenomenon, various methods have been proposed. Among these methods are, an STI method using a pull back process, which is disclosed in Korean Patent Application No. 98-21,037. According to that Korean Patent Application, after forming a trench as shown on
FIG. 1
, an etch protecting layer
13
covering an active region is isotropically etched to form a reduced pattern
13
′ which exposes a portion of the active region around the trench
15
as shown in FIG.
5
. Then, an inner wall of the trench
15
is oxidized to form an inner wall oxide film
17
to a thickness of 150 to 300 Å. Thereafter, a silicon nitride film as a liner
19
is formed. As the liner
19
is formed, the portion of the active region around the trench
15
is almost covered with the liner
19
, as shown in FIG.
6
.
Next, a CVD silicon oxide layer
21
is deposited over the substrate
10
to fill the trench
15
. Then, a portion of the CVD silicon oxide layer
21
formed over the etch protecting layer
13
in an active region is removed by planarization etching. Thereafter, the reduced pattern
13
′ is wet-etched. At this time, a top end of the liner
19
covering the portion of the active region around the trench
15
is removed, but a portion of the liner
19
formed on the inner wall of the trench
15
remains, as shown in FIG.
7
. Thus, the ‘dent’ phenomenon of forming the concave space in the vicinity of the top end of the inner wall of the trench
15
can be prevented.
However, in the STI method using the pull back process, a top end of the inner wall of the trench
15
, i.e., an edge portion of the upper surface of the substrate in the active region is covered with the liner
19
′ and the inner wall oxide film
17
, so that when a gate insulating film is formed after removing the etch protecting layer and the pad oxide film
11
, oxygen is not supplied thereto very well. Accordingly, an oxide layer forming the gate insulating film is thinly formed on the edge portion of the upper surface of the substrate in the active region in the vicinity of the top end of the inner wall of the trench
15
compared with that on the other portion. This may result in problems of reducing the value of the breakdown charge Qbd to deteriorate the reliability in the insulation, and generating the leakage current.
Also, in other method for preventing the ‘dent’ phenomenon, an edge portion of the upper surface of the substrate in the active region is also protected very well, so that it comes to have an angled shape while the etching processes for forming trenches are carried out. When the edge portion has an angular shape, the high electric field can be concentrated thereto, thereby resulting in the insulation damage or the current leakage.
SUMMARY OF THE INVENTION
It is a feature of an embodiment of the present invention to provide an improved STI type semiconductor device and method of forming the same, which can prevent the ‘dent’ phenomenon and decrease the degradation in the transistor characteristic resulting from the substrate having an angled shape at an edge portion of the upper surface of a substrate in an active region.
This and other features are provided, according to the present invention, by an STI type semiconductor device comprising at least one trench formed on a silicon substrate to define at least one active region, a silicon thermal-oxide film formed on

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