Shallow trench isolation (STI) and method of forming the same

Details Shallow trench isolation (STI) and method of forming the same Shallow trench isolation (STI) and method of forming the same

2000-11-06

2002-11-12

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S248000, C438S295000, C438S424000, C438S426000, C438S702000

Reexamination Certificate

active

06479369

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a shallow trench isolation (STI) in a semiconductor substrate and a method of forming the same, and more particularly to a shallow trench isolation where recesses are not formed at a surface of an oxide film filled in a trench formed in a semiconductor substrate, and method of forming such a shallow trench isolation.
2. Description of the Related Art
When devices formed on a semiconductor substrate have to be electrically isolated from one another, those skilled in the art often select shallow trench isolation (hereinbelow, referred so simply as “STI”) where a trench is formed at a surface of a semiconductor substrate and the trench is filled with an insulating film.
FIGS. 1A
to
1
G are cross-sectional views of STI fabricated by a conventional method.
First, as illustrated in
FIG. 1A
, a trench mask pattern
16
comprised of a silicon dioxide film
12
formed by thermal oxidation and a silicon nitride film
14
is formed on a semiconductor substrate such as a silicon substrate
10
.
Then, as illustrated in
FIG. 1B
, the silicon substrate
10
is etched by dry etching through the use of the mask pattern
16
to thereby form a trench
18
.
Then, as illustrated in
FIG. 1C
, the silicon substrate
10
is thermally oxidized to thereby form a silicon dioxide film
20
covering a bottom and a sidewall of the trench
18
.
Then, as illustrated in
FIG. 1D
, a silicon dioxide film
22
is formed over the product illustrated in
FIG. 1C
such that the trench
18
is entirely filled with the silicon dioxide film
22
.
Then, as illustrated in
FIG. 1E
, the silicon dioxide film
22
is polished by chemical mechanical polishing (CMP) until the silicon nitride film
14
appears. That is, the silicon nitride film
14
is used as a polishing stopper.
Then, as illustrated in
FIG. 1F
, the silicon nitride film
14
is removed by wet etching.
Then, as illustrated in
FIG. 1G
, the silicon dioxide film
12
and a portion of the silicon dioxide film
22
are removed by wet etching such that the silicon dioxide film
22
is on a level with the silicon substrate
10
.
Thus, there is completed STI wherein the trench is filled with the silicon dioxide film
22
.
Since the wet etching is isotropically carried out in the step illustrated in
FIG. 1G
, a portion
24
(see
FIG. 1F
) at which a sidewall of the silicon dioxide film
22
meets the silicon dioxide film
12
is most aggressively etched. As a result, as illustrated in
FIG. 1G
, recesses
26
are formed at a surface of the silicon dioxide film
22
filling the trench
28
therewith.
For instance, when the silicon dioxide film
22
has a depth in the range of 300 to 400 nm, the recesses
26
would have a depth of about 50 nm.
In the above-mentioned conventional method of fabricating STI, it is unavoidable that the recesses
26
are formed at a surface of the silicon dioxide film
22
filling the trench
18
therewith. The recesses
26
cause a problem as follows.
It is assumed that MOSFET is fabricated on the silicon substrate
10
. If a gate electrode of MOSFET is formed on STI, the recess
26
creates regions of high electric field at corners of the recess
26
, and hence, a threshold voltage at the corners of the recess
26
is reduced. This results in hump or kink phenomenon in the Id-Vg characteristic of MOSFET, further resulting in poor performance of MOSFET.
Such a problem as mentioned above is indicated in the following documents, for instance:
(A) C. Chen et al., 1996 IEDM Tech. Digest, pp 837-840;
(B) H. Perera et al., 1995 IEDM Tech. Digest, pp 679-682; and
(C) M. Nandakumar et al., 1998 IEDM Tech. Digest, pp 133-136.
In addition, if the recesses
26
had an extremely great depth, etching residue would remain when a gate electrode is etched, resulting in a problem of shortcircuit between gate wirings.
Many attempts have been made to fabricate STI where recesses are not formed at a surface of a silicon dioxide film filling a trench therewith.
For instance, a method in which a silicon dioxide film filling a trench therewith is T-shaped such that ends of the silicon dioxide film are located outside a trench has been suggested in the following documents:
(A) P. C. Fazan et al., 1993 IEDM Tech. Digest, pp 57-60;
(B) W. K. Yeh et al., 1998 SSDM, pp 98-99;
(C) T. Park et al., 1996 IEDM Tech. Digest, pp 675-678;
(D) A. Chatterjee et al., 1996 IEDM Tech. Digest, pp 829-832; and
(E) T. Yamazaki et al., 1999 SSDM, pp 18-19.
A method in which a trench is formed after a gate electrode has been formed is suggested in the following document:
(F) C. Chen et al., 1996 IEDM Tech. Digest, pp 837-840.
However, it is not always possible even by the above-mentioned methods to perfectly prevent formation of the recesses
26
at a surface of the silicon dioxide film
22
.
In the conventional method of fabricating STI, having been explained with reference to
FIGS. 1A
to
1
G, the silicon dioxide film
22
illustrated in
FIG. 1D
may be thermally annealed at a temperature equal to or greater than 1000 degrees centigrade to densify the silicon dioxide film
22
in order to enhance a resistance of the silicon dioxide film
22
against wet etching, or reduce an etching rate of the silicon dioxide film
22
for preventing the formation of the recesses
26
.
However, if the silicon dioxide film
22
were thermally annealed, the silicon dioxide film
22
would be contracted, resulting in that stresses are generated in the silicon substrate
10
, and hence, crystal defects are generated. If the silicon dioxide film
22
were thermally annealed at about 800 degrees centigrade so that small stresses are generated in the silicon substrate
10
, it would be impossible to enhance a resistance of the silicon dioxide film
22
to etching.
SUMMARY OF THE INVENTION
In view of the above-mentioned problems in the conventional methods, it is an object of the present invention to provide a method of fabricating a shallow trench isolation which is capable of preventing the formation of recesses at a surface of an oxide film filling a trench therewith, and further preventing generation of stresses in a semiconductor substrate.
It is also an object of the present invention to provide a shallow trench isolation which is capable of doing the same.
In one aspect, there is provided a method of forming a shallow trench isolation, including the steps, in sequence, of (a) forming a trench in a semiconductor substrate, (b) forming a first oxide film covering an inner surface of the trench such that the trench is not filled with the first oxide film, (c) heating the first oxide film, (d) forming a second oxide film over a product resulted from the step (c) such that the trench is filled with the second oxide film, and (e) etching the first and second oxide films such that the first and second oxide films are on a level with a surface of the semiconductor substrate.
In accordance with the present invention, an oxide film filling a trench therewith is designed to have a two-layered structure including the first oxide film and the second oxide film. The first oxide film is designed to have such a thickness that a trench is not filled with the first oxide film. That is, the first oxide film is formed in the step (b) to have a thickness smaller than a half of a width of the trench. The first oxide film is then heated to be densified and have an enhanced resistance to etching. Though the first oxide film is contracted in the heating step (c), a contract stress is absorbed into the first oxide film, because a space exists adjacent to the first oxide film in the trench. Hence, there is not generated a stress in the semiconductor substrate.
It is preferable that the first oxide film is heated in the step (c) at a temperature equal to or greater than 900 degrees centigrade in order to enhance a resistance of the first oxide film to etching. It is also preferable that the first oxide film is heated in the step (c) at a temperature equal to or smaller than 1200 degrees centigrade in order to prevent curvature of the

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