Shallow trench isolation spacer for weff improvement

Details Shallow trench isolation spacer for weff improvement Shallow trench isolation spacer for weff improvement

2001-12-27

2003-05-20

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S700000

Reexamination Certificate

active

06566230

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor processing, and more particularly to a method for performing trench isolation during semiconductor device fabrication.
BACKGROUND OF THE INVENTION
Shallow trench isolation (STI) technology uses shallow, refilled trenches for isolating devices of the same type as replacements for LOCOS isolation. The process begins by depositing a layer of thermal oxide on a silicon substrate and patterning a nitride mask to define active regions on the silicon substrate. Shallow trenches are then etched into the silicon substrate in the openings in the nitride mask between the active areas. A liner oxidation process is performed in the recesses in which a thin layer of thermal oxide is grown. Next, a dielectric oxide (e.g., SiO2) is deposited over the silicon substrate to fill the trenches. This oxide is etched back and polished off until it is at the same level as the nitride mask. Then the nitride mask is stripped to expose the thermal oxide on the active areas and wet etches are done to recess back the dielectric material from the active areas. Thereafter, a layer of polysilicon (Poly1) may be patterned to define floating gate structures for the semiconductor device.
Although the STI process has the advantages of eliminating birds beak of the LOCOS process and of providing a planar surface, the STI process has several drawbacks.
FIGS. 1A and 1B
are block diagrams showing a cross-sectional view of a silicon substrate
10
processed by the conventional STI process. Shallow trenches
12
have been etched into a silicon substrate between active areas
14
in the substrate under the nitride mask
16
. One goal during semiconductor processing is to have the base for the active areas
14
to be as wide as possible to increase W effective (Weff) for the device. Weff being the resulting effective active width after silicon consumption by liner oxidation and various subsequent wet etch cleans and oxidation processes. A wider Weff helps to improve the electrical core gain or drain to source current (Ids) for the device.
While the initial liner oxidation performed in the trenches serve the important purpose of active area corner rounding and the subsequent dip back cleans and oxidation processes are necessary for forming a clean active area surface, they do result in Si consumption, hence reducing the effective active area width (Weff) as shown in FIG.
1
B. One solution to achieve a wider Weff is to simply pattern the nitride mask
16
wider to form a wider base for the active area
14
. This, however, results in a much narrow region between active areas
14
that may pose lithography patterning limitations.
Accordingly, what is needed is an STI process that improves Weff without posing lithography patterning limitations. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method for performing trench isolation during semiconductor device fabrication. The method includes patterning a hard mask to define active areas and isolations areas on a substrate, and forming spacers along edges of the hard mask. Trenches are then formed in the substrate using the spacers as a mask.
According to the system and method disclosed herein, forming spacers along the hard mask edges subsequent to the patterning of the hard mask for trench formation results in a wider initial silicon base for the active areas. Consequently, a wider active Si width (Weff) is obtained after liner oxidation and subsequent dip back cleans and oxidations.


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patent: 2000-31262 (2000-01-01), None
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