Shallow trench isolation scheme for border-less contact process

Details Shallow trench isolation scheme for border-less contact process Shallow trench isolation scheme for border-less contact process

2001-12-03

2004-05-25

Chen, Kin-Chan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S706000

Reexamination Certificate

active

06740592

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing junction leakage in a border-less contact processes in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, shallow trench isolation (STI) is often used to isolate active areas from one another. In order to shrink cell size, border-less contact is one of the most important processes in the art. Of major concern is the border-less contact leakage current for shallow junctions, especially at the edge of the STI regions. It is desired to find a method of preventing leakage at the edge of STI regions in a border-less contact process.
Co-pending U.S. patent application Ser. No. 09/489,967 (TSMC-99-241) to K. B. Thei et al, filed on Jan. 24, 2000 discloses a method of depositing an etch stop layer over a salicide layer and densifying this layer. This etch stop layer prevents leakage at the STI edges during border-less contact formation. Co-pending U.S. patent application Ser. No. 09/398,293 (TSMC-98-633) to L. Lui, filed on Sep. 20, 1999, teaches forming an etch stop lining layer within via openings to protect the via sidewalls during etching of a trench opening in the formation of a dual damascene opening. U.S. Pat. No. 6,046,103 to Thei et al discloses an etch stop layer formed overlying a silicide layer. U.S. Pat. No. 5,652,176 to Maniar et al shows an aluminum nitride isolation trench liner that prevents junction leakage during border-less contact etching. U.S. Pat. No. 5,447,884 to Fahey et al teaches a nitride STI liner layer that is densified. U.S. Pat. No. 6,121,064 to Lasky et al shows a light-absorbing liner layer of hydrosilicon oxynitride. U.S. Pat. No. 4,533,429 to Josquin and 4,845,048 to Tamaki et al show silicon nitride liner layers on the sidewalls of a trench in a LOCOS process.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method for forming a border-less contact in the fabrication of integrated circuits.
It is a further object of the invention to provide a border-less contact process while avoiding current leakage at the shallow trench isolation edge in the fabrication of integrated circuits.
Yet another object is to provide a method for avoiding current leakage at the shallow trench isolation edge by forming an etch stop liner film on the sidewalls of the STI trench to protect the STI edge during borderless contact etching.
In accordance with the objects of the invention, a method for avoiding current leakage at the shallow trench isolation edge in a border-less contact process is achieved. Trenches are etched into a semiconductor substrate. An etch stop liner layer is deposited within the trenches and etched back to leave the etch stop liner layer only on sidewalls of the trenches to form liner sidewalls. The trenches are filled with an isolation layer overlying the liner sidewalls to complete formation of shallow trench isolation trenches separating active areas of the semiconductor substrate. Semiconductor device structures are formed in the active areas wherein the semiconductor device structures include source and drain junctions. An interlevel dielectric layer is deposited over the semiconductor device structures. Border-less contact openings are etched through the interlevel dielectric layer wherein the liner sidewalls act as an etch stop during this etching thereby preventing leakage of the source and drain junctions. The contact openings are filled with a conducting layer wherein the liner sidewalls act as a diffusion barrier to the conducting layer to form interconnects to complete fabrication of the integrated circuit device.


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Co-pending U.S. patent application Ser. # 09/398,293 (TSMC-98-633) to L. Lui, filed on Sep. 20, 1999.

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