Shallow trench isolation method used in a semiconductor wafer

Details Shallow trench isolation method used in a semiconductor wafer Shallow trench isolation method used in a semiconductor wafer

1999-08-23

2001-02-20

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S401000, C438S427000

Reexamination Certificate

active

06191000

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a shallow trench isolation method used in a semiconductor wafer.
2. Description of the Prior Art
Either a localized oxidation isolation (LOCOS) method or a shallow trench isolation method is typically used in semiconductor manufacturing to isolate electronic components from each other so as to prevent short-circuiting. Since the field oxide and bird's beak generated by the LOCOS process occupies a very large area on the semiconductor wafer, the shallow trench isolation method is used for most advanced semiconductor manufacturing processing. In the shallow trench isolation method, isolation of components is achieved by carving shallow trenches in between elements on the surface of wafer then filling the trenches with isolation material. This results in electrical isolation of the components. The regions between adjacent trenches are called active regions.
FIG.
1
and
FIG. 2
are schematic diagrams of cross-sectional views of the semiconductor wafer used to perform the manufacturing process of the shallow trench isolation of the prior art. In the fabrication of the wafer
10
, a wafer alignment region
16
is first defined on the silicon substrate
20
of the wafer
10
prior to performing shallow trench isolation. This is labeled as region A in
FIG. 1. A
plurality of recesses
18
having a predetermined pattern is formed in the wafer alignment region
16
to be used as standard reference points for the stepper. This ensures precision in the transfer of the mask pattern onto the surface of the wafer
10
during the photolithography process. Afterwards, a silicon oxide layer
22
and a silicon nitride layer
24
are formed in sequence on the silicon substrate
20
. This is then followed by the formation of a plurality of active regions
14
and their isolating shallow trenches
12
by removing a predetermined region of the silicon nitride layer
24
and silicon oxide layer
22
as well as a predetermined depth of the silicon substrate
20
on the wafer
10
. Region B in
FIG. 2
is the working region
28
and has a relatively high density of active regions
14
.
FIGS. 3 through 6
are schematic diagrams of the shallow trench isolation method in a semiconductor manufacturing process of the prior art. The manufacturing process of the shallow trench isolation proceeds following the completion of the fabrication of the wafer
10
and its shallow trenches
12
. As shown in
FIG. 3
, in the prior art method of shallow trench isolation, an insulation layer
26
is first formed on the surface of the wafer
10
that fills the shallow trenches
12
and the recesses
18
. Then, as shown in
FIG. 4
, an etching process is implemented to remove a predetermined thickness of the insulation layer
26
from the surface of the active regions
14
and the wafer alignment region
16
. As shown in
FIG. 5
, a chemical mechanical polishing (CMP) process is then performed to remove the insulation layer
26
from the surface of the wafer
10
such that the surface of the insulation layer
26
in each shallow trench
12
is flush with the surface of the silicon nitride layer
24
. Finally, as shown in
FIG. 6
, a photolithographic process and a wet etching process are applied to the wafer alignment region
16
to completely remove the insulation layer
26
from the recesses
18
to complete the shallow trench isolation process.
As shown in
FIG. 4
, since the density of active regions
14
in the working region
28
is relatively high, the average thickness of the insulation layer
26
is higher in the working region
28
than outside of the working region following removal of the insulation layer
26
to a predetermined thickness through etching of the wafer
10
. As shown in
FIG. 5
, this makes it difficult for the surface of the insulation layer
26
in the shallow trenches
12
of the working region
28
to be level with the surface of the silicon nitride layer
24
after subsequent CMP processing. However, excessive polishing in order to keep the surface of the insulation layer
26
in the shallow trenches
12
at the same level as the surface of the silicon nitride layer
22
will result in the insulation layer
26
being excessively low in the shallow trenches
12
outside the working region
28
. This will consequently affect the electrical isolation effect.
SUMMARY OF THE INVENTION
Therefore, the primary objective of the present invention is to provide a shallow trench isolation method such that the thickness of the insulation layer in each shallow trench will not be affected by different densities of the active regions, and the method of the present invention can completely remove the insulation layer from the recesses of the wafer alignment region.
The shallow trench isolation (STI) method used in a semiconductor wafer wherein the surface of the semiconductor wafer comprising a plurality of active regions, a plurality of shallow trenches for electrically isolating the active regions and an alignment region having at least a recess of predetermined pattern therein comprises the following steps:
1. Forming an insulation layer on the surface of the semiconductor wafer that completely fills the trenches and the recess in the alignment region.
2. Etching the insulation layer on the active regions and alignment region to a predetermined thickness.
3. Defining at least one working area on the surface of the semiconductor wafer over which the density of the active regions in the working area is higher than that of the active regions outside the working area, and etching the insulation layer on the working area and the alignment region to reduce the thickness of the insulation layer on the working area and to completely remove the insulation layer on the alignment region.
4. Performing a chemical mechanical polishing process to horizontally remove the insulation layer on the surfaces of the active regions and to approximately level the surfaces of the insulation layer in the trenches with the surfaces of the active regions.
It is an advantage of the present invention that the thickness of the insulation layer does not vary with shallow trench density in the working region and the insulation layer within the shallow trenches are therefore flush with the wafer surface without excessive polishing. This leads to better electrical isolation.
These and other objects and the advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
patent: 5721172 (1998-02-01), Jang et al.
patent: 5880007 (1999-03-01), Varian et al.
patent: 5889335 (1999-03-01), Kuroi et al.
patent: 5998279 (1999-12-01), Liaw
patent: 6043133 (2000-03-01), Jang et al.
patent: 6057210 (2000-05-01), Yang et al.
patent: 6060370 (2000-05-01), Hsia et al.

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