Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-04-07
1998-10-06
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438424, 438435, 438437, 438642, 148DIG50, H01L 2176
Patent
active
058175679
ABSTRACT:
An improved method for implementing shallow trench isolation in integrated circuits is described. The method begins with the formation of trenches, through patterning and etching. These trenches are then filled with a conformal layer of silicon oxide. This is followed by overcoating with a layer of a hard material such as silicon nitride or boron nitride. Next, chemical-mechanical polishing is used to remove the hard layer everywhere except where it has filled the depressions that overlie the trenches. Then, a non-selective etch is used to remove the remaining hard layer material as well as some of the silicon oxide, so that a planar surface is maintained. Finally, chemical-mechanical polishing is used a second time to remove excess silicon oxide from above the trenches' surface.
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Chen Ying-Ho
Jang Syun-Ming
Yu Chen-Hua
Ackerman Stephen B.
Dang Trung
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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