Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-10-14
2000-11-07
Fourson, George
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438426, 438435, 438766, 438966, 438981, H01L 21762
Patent
active
061436240
ABSTRACT:
An insulated trench isolation structure is formed by ion implanting impurities proximate the trench edges to enhance the silicon oxidation rate and, hence, increase the thickness of the resulting oxide at the trench edges. Embodiments include masking and etching a barrier nitride layer, forming protective spacers on portions of the substrate corresponding to subsequently formed trench edges, etching the trench, removing the protective spacers, ion implanting impurities into those portions of the substrate previously covered by the protective spacers, and then growing an oxide liner. The resulting oxide formed on the trench edges is thick due to the enhanced silicon oxidation rate, thereby avoiding overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.
REFERENCES:
patent: 4693781 (1987-09-01), Leung et al.
patent: 4923821 (1990-05-01), Namose
patent: 6001707 (1999-12-01), Chih-Hung
patent: 6063694 (2000-05-01), Mitsuhiro
Bandyopadhyay Basab
Ibok Effiong
Karlsson Olov
Kepler Nick
Lyons Christopher F.
Advanced Micro Devices , Inc.
Fourson George
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