Shallow trench isolation chemical-mechanical polishing process

Details Shallow trench isolation chemical-mechanical polishing process Shallow trench isolation chemical-mechanical polishing process

2000-02-18

2002-07-23

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

C257S501000, C257S506000, C257S752000

Reexamination Certificate

active

06424019

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to shallow trench isolation (STI) processes employed in the fabrication of integrated circuits (ICs). The present invention more particularly relates to modified shallow trench isolation (STI) processes that include forming composite layered stacks become chemical-mechanical polishing of the integrated circuit (IC) substrate surfaces.
As the current IC technology moves to smaller feature sizes and the density of IC features in an IC substrate surface increases, STI processes are replacing the local oxidation of silicon (LOCOS) isolation methods as the process of choice for isolating active areas in Complementary Metal Oxide Semiconductor (CMOS) circuits, for example. Local oxidation of silicon (LOCOS) isolation methods are undesired at sub-0.5 &mgr;m dimensions and lower because they typically introduce non-planarity and a “bird's beak” at the edge of an active area and therefore reduce the packing density of the circuitry. In contrast, STI processes provide isolation schemes that produce a relatively high degree of planarity and eliminate the bird's beak to dramatically reduce the chip area required for isolation.
FIGS. 1A-C
show some major steps of a conventional STI process that may be employed to fabricate trenches in the IC substrate. In order to form a partially fabricated IC substrate
10
(hereinafter referred to as “IC substrate”) as shown in
FIG. 1A
, a native oxide layer
24
, e.g., a silicon dioxide layer, is blanket deposited on a surface of an IC substrate layer
12
. A polishing stopping mask layer
14
, e.g., a silicon nitride layer (Si
3
N
4
), is then blanket deposited over native oxide layer
24
.
Next, polishing stopping layer
14
, native oxide layer
24
and IC substrate layer
12
are etched through using conventional photolithography techniques well known to those skilled in the art to form trenches
18
,
20
and
22
in IC substrate layer
12
. Trench
22
is formed in a wide open area and trenches
18
and
20
are formed in a dense area of IC substrate
10
. The dense area, as shown in
FIG. 1A
, has a greater number of trenches per unit area of the IC substrate surface than the wide open area. Those skilled in the art will also recognize that the trenches in the wide open area are also wider than the trenches in the dense area.
An insulating layer
16
, e.g., a silicon dioxide layer, is then deposited either by chemical vapor deposition (CVD) or spin-on glass (SOG), for example, on IC substrate
10
filling trenches
18
,
20
and
22
with the insulating layer so that subsequently formed active areas in IC substrate
10
are electrically isolated from each other. As shown in
FIG. 1A
, a portion of insulating layer
16
is also deposited above polishing stopping layer
14
and this portion of insulating layer
16
is referred to as the “insulating layer overburden.”
IC substrate
10
is then subject to chemical-mechanical polishing (CMP) to remove the insulating layer overburden and polishing stopping layer
14
. CMP typically involves mounting an IC substrate face down on a holder and rotating the IC substrate face against a polishing pad mounted on a platen, which in turn is rotating or is in orbital state. Those skilled in the art will recognize that because insulating layer
14
typically includes SiO
2
, “oxide CMP” (which refers to the CMP process for polishing SiO
2
) is typically carried out in this step. During oxide CMP, a slurry composition including H
2
O
2
(hydrogen peroxide), for example, is introduced between the polishing pad and an IC substrate surface or on the polishing pad near the IC substrate to remove SiO
2
.
FIG. 1B
shows an intermediate structure that is formed during oxide CMP after the insulating layer overburden is removed and polishing stopping layer
14
is exposed. The presence of polishing stopping layer
14
ensures that after oxide CMP has concluded, an appropriate thickness of native oxide layer
24
is maintained above IC substrate layer
12
. Those skilled in the art will recognize that a thickness of a native oxide layer has a significant impact on the performance characteristics of an IC.
As shown in
FIG. 1B
, after the insulating layer overburden is removed, the surface of insulating layer
16
above trenches
18
and
20
is substantially planar. Above trench
22
, however, near or about a middle region of the surface of insulating layer
16
(in the wide open area), a concave region or an indented region
26
may be formed. Concave region
26
recesses inwardly into the surface of insulating layer
16
and is referred to as “dishing” because the profile of the concave region resembles the profile of a dish. The degree of dishing can be quantified by measuring the distance between the center of the surface of insulating layer
16
(above trench
22
), which is typically the lowest point of the concave region, and the point where the insulating layer levels off, which is typically the highest point of the concave region.
After oxide CMP has concluded and polishing stopping layer
14
is removed, isolation structures (i.e. trenches
18
,
20
and
22
filled with insulating material
16
) are formed below the IC substrate layer
12
, native oxide layer
24
with the appropriate thickness is maintained above the IC substrate layer and the substantially planar surface of insulating layer
16
above trenches
18
and
20
is preserved, as shown in FIG.
1
C. The degree of dishing, however, in the wide open area above trench
22
may increase and the resulting concave region shown in
FIG. 1C
by reference numeral
26
′ may recess inwardly into the surface of insulating layer
16
to a greater extent because during oxide CMP a material removal rate of the insulating layer (e.g., SiO
2
) is higher than a material removal rate of the polishing stopping layer (e.g., Si
3
N
4
). Thus, oxide CMP has a high selectivity to the polishing stopping layer. After the isolation structures shown in
FIG. 1C
are formed the IC fabrication process typically proceeds to forming IC features of active areas, e.g., transistor devices.
Unfortunately, the conventional STI process described above fails to provide trench isolation structures that effectively isolate active areas from each other. By way of example, the undesirable effect of dishing described above in detail may provide an electrically conductive pathway to charge carriers in a CMOS circuitry between a p-type doped region that may be disposed on one side of trench
22
and a n-type doped region that may be disposed on the other side of trench
22
. As a result, electrical leakage over a period of time may result to catastrophic IC failure.
What is therefore needed is an improved STI process that reduces the likelihood of dishing and produces isolation structures or trenches filled with an insulating material having substantially planar surfaces that effectively isolate active areas in an IC from each other.
SUMMARY OF THE INVENTION
To achieve the foregoing, in one aspect, the present invention provides a process for fabricating a trench filled with an insulating material in a surface of an integrated circuit substrate. One step of the process includes defining a masking layer on a composite layered stack above a region to be protected on the integrated circuit substrate surface. The composite layered stack includes a layer of a first material and a polishing stopping layer. The layer of the first material has a polishing rate by chemical mechanical polishing that is greater than a polishing rate by chemical mechanical polishing of the insulating material. Another step of the process includes etching through the composite layered stack and the integrated circuit substrate to form the trench in the integrated circuit substrate surface and depositing the insulating material on the integrated circuit substrate surface such that the trench is filled with the insulating material. A yet another step of the process includes polishing the integrated circuit substrate surface to remove a substantial por

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