Shallow trench isolation

Details Shallow trench isolation Shallow trench isolation

1998-07-10

2000-11-14

Hardy, David

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438436, 438435, 438433, 438427, 438424, 438401, 438296, 257510, H01L 2176, H01L 2900

Patent

active

061469750

ABSTRACT:
The specification describes a dual patterned polish stop layer technique for shallow trench isolation. The shallow trenches are formed by etching trenches in a semiconductor substrate wafer, backfilling with oxide, and polishing by chemical-mechanical polishing (CMP) to produce a planar, trench isolated, wafer. To ensure planarity of the wafer after CMP, and avoid dishing of the field oxide, a dual silicon nitride polish stop layer is used. The first polish stop layer is applied selectively to protect the active device regions, and the second polish stop layer is applied selectively to protect the field oxide regions.

REFERENCES:
patent: 5362669 (1994-11-01), Boyd et al.
patent: 6001706 (1999-12-01), Tan et al.

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