Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-04-04
2001-09-04
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S154000
Reexamination Certificate
active
06285575
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates generally to a shadow RAM (Random Access Memory) cell and a non-volatile memory device employing a ferroelectric capacitor and a control method therefor. More particularly, the invention relates to a shadow RAM having a memory cell fabricated by adding a ferroelectric capacitor to a SRAM (Static RAM) cell, performing reading and writing operation at high speed in the SRAM while power is supplied, and storing data in non-volatile manner by the ferroelectric capacitor while power is not supplied.
2. Description of the Related Art
Conventionally, there have been proposed a plurality of shadow RAMs, in which the ferroelectric capacitors and the SRAM cells are combined. These shadow RAM cells store information by the SRAMs while power is supplied, for permitting high speed reading and writing comparable with common SRAM. In addition, by transferring information stored in the SRAM cells in polarizing direction of the ferroelectric capacitor before shutting down of the power source, non-volatile storage is realized. Namely, the shadow RAM employing the ferroelectric capacitor is a storage device achieving non-volatile storage ability of the ferroelectric memory and high speed operation of the SRAM.
For example, a construction of the memory cell of the shadow RAM employing the ferroelectric capacitor disclosed in Japanese Unexamined Patent Publication No. Heisei 4-57291 has a construction shown in FIG.
7
. Two inverters (logical inverting elements)
1
and
2
form a flip-flop (F/F)
3
by mutually connecting input and output thereof. Tow storage nodes Q
0
and Q
1
of the flip-flop
3
are connected to a negative bit line BLN and a positive bit line BLT via NMOS transistors M
0
and M
1
serving as transfer gates respectively. These two positive and negative bit lines for a pair. To one end of a pair of positive and negative bit lines, a sense amplifier (not shown) comparing voltages thereof is connected.
Also, a writing circuit (not shown) selectively connecting either bit lines to a ground potential upon writing and a pre-charge circuit (not shown) for pre-charging the bit line to a power source potential or the ground potential are connected to the bit line. Gate electrodes of the NMOS transistors M
0
and M
1
are connected to a common word line WL. The word line WL is connected to a decoder circuit (not shown) for selectively driving one word line to be an object for access according to an address signal. Ferroelectric capacitors F
0
and F
1
connected to a common plate line PL at one end, are provided. The other ends N
0
and N
1
of the ferroelectric capacitors F
0
and F
1
are connected to the storage nodes Q
0
and Q
1
via NMOS transistors M
2
and M
3
serving as transfer gates.
Gate electrodes of the transistors M
2
and M
3
are connected to a common control line CL. The control line CL becomes HIGH level only during storing operation and recalling operation, in which the ferroelectric capacitors F
0
and F
1
are accessed, for connecting the flip-flop
3
and the ferrorelectric capacitors F
0
and F
1
, respectively. In other states while power is supplied, the control line CL is held LOW level to electrically disconnect the flip-flop
3
and the ferroelectric capacitors. On the other hand, the plate line PL is maintained at LOW level while the control line CL is held at LOW level.
Next, operation of the conventional shadow RAM employing the ferroelectric capacitor will be discussed. It should be clear that writing and reading of information in and from the flip-flop
3
is similar to the conventionally typical SRAM. During idling while neither reading nor writing is performed, the bit line is pre-charged at HIGH level to lower potential at all word lines to disable the writing circuit and whereby to maintain information in the flip-flop
3
.
For writing information in the flip-flop
3
, an appropriate word line WL is risen by an address decoder. At the same time, the writing circuit is driven to make one of the bit lines BLT and BLN forming a pair into Low level according to data to write. When the word line WL i s risen, the MOS transistors M
0
and M
1
are turned ON. Since driving performance of the writing circuit is sufficiently larger than that of the inverters
1
and
2
, the storage nodes connected to the bit lines drawn into LOW level by the writing circuit via the MOS transistor, is drawn into the ground potential. At the same time, the other storage node is pulled up to the power source voltage. Thus, the flip-flop
3
becomes stable.
On the other hand, reading of data from the flip-flop
3
is performed by selecting an appropriate word line and by amplifying a potential difference appearing on the selected bit line by the sense amplifier after pre-charging the bit line pair to HIGH level. By rising the word line WL, the MOS transistor connecting the storage node held at LOW level and the bit line, is turned ON to start lowering of the voltage of the relevant bit line. Since the MOS transistors of other bit lines are not turned ON, those bit lines are held HIGH level. By making judgment of potential difference of the bit lines forming a pair by the sense amplifier, information stored in the flip-flop can be read out.
Next, storing operation will be discussed with reference to
FIGS. 8 and 9
.
FIG. 8
shows a hysteresis characteristics on a Q-V plane of ferroelectric capacitors F
0
and F
1
, and
FIG. 9
is a timing chart of waveforms of respective part in storing operation. Upon shutting down of the power source, data stored in the flip-flop is transferred to polarizing direction of the ferroelectric capacitors F
0
and F
1
. This operation will be referred to as storing. Storing is activated in response to a store signal input in advance of lowering or shutting down of the power source. Storing is performed in the following procedure.
At first, the control line CL becomes HIGH level to electrically connect the flip-flop
3
and the ferroelectric capacitors F
0
and F
1
. At this time, the plate line PL is held LOW level, 0V is applied to one of the ferroelectric capacitors connected to the storage node of 0V, and, on the other hand, a voltage of (Vcc−Vt) is applied on the side connected to the storage node of the power source voltage (Vcc). Here, Vt is a threshold voltage of the MOS transistors M
2
and M
3
. When Vcc is applied to the control line CL, the voltage to be applied to the capacitor becomes (Vcc−Vt).
The voltages Vc
0
and Vc
1
respectively applied to the ferroelectric capacitors F
0
and F
1
are defined as potential differences between the potential on the terminal connected to the MOS transistors M
2
and M
3
and the potential of the terminal connected to the plate line PL. The voltage (Vcc−Vt) applied to the ferroelectric capacitor is shifted to a point A′ of a hysteresis loop shown in FIG.
8
.
Next, the plate line PL is risen to Vcc. At this time, the voltage applied to the ferroelectric capacitor to be applied the voltage (Vcc−Vt) at first becomes Vcc at both ends. This is because that since the transistors M
2
and M
3
are turned OFF to cause capacitive coupling by the ferroelectric capacitors to elevate the potential on the side of the transistor together with potential elevation of the plate line PL. Accordingly, the voltage to be applied to the ferroelectric capacitor becomes 0V to hold positive residual dielectric polarization (point B′). To the other ferroelectric capacitor, −Vcc is applied to shift to a point C of the hysteresis loop shown in FIG.
8
.
Finally, the control line CL and the plate line PL are fallen down. Subsequently, the power source is shut down. After shutting down of the power source, respective nodes are converged to the ground potential. Accordingly, finally, the ferroelectric capacitor located at the point C is shifted to a point D to hold negative residual dielectric polarization. Since the ferroelectric capacitor may maintain the residual dielectric polarization for ten year
Hutchins, Wheeler & Dittmer
Lam David
NEC Corporation
Nelms David
LandOfFree
Shadow RAM cell and non-volatile memory device employing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Shadow RAM cell and non-volatile memory device employing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shadow RAM cell and non-volatile memory device employing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2448665