Several improvements for timing diagrams

Details Several improvements for timing diagrams Several improvements for timing diagrams

2001-09-17

2004-06-01

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06745376

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method used to display signals in electronic systems, and more specifically to a method for graphically representing temporal relationships between signals.
BACKGROUND OF THE INVENTION
In today's high performance electronic systems, timing continues to be a top priority. As a result, designers are spending increased effort addressing integrated circuit (IC) performance. Traditionally, dynamic simulators have been utilized to verify the functionality and timing of an entire design or blocks within the design. Dynamic timing simulation requires vectors, a logic simulator and timing information. With this methodology, input vectors are used to exercise functional paths based on dynamic timing behaviors for the chip or block.
The advent of larger designs and huge vector sets make dynamic simulation a serious bottleneck in design flows. Dynamic simulation is becoming more problematic because of the difficulty in creating comprehensive vector sets with high levels of coverage. Time-to-market pressure, chip complexity, limitation in the speed and capacity of traditional simulators all are motivating factors for migration toward static timing techniques.
Static timing analysis (STA) is an exhaustive method of analyzing, debugging and validating the time performance of a design. First, a design is analyzed, then all possible paths are timed and checked against the requirements. Since STA is not based on functional vectors, it is typically very fast and can accommodate very large designs. STA is exhaustive in that every path in the design is checked for timing violations. This is a key advantage over dynamic simulators, which require an impossible number of vectors in order to provide the same level of timing coverage.
STA typically generates several textual reports identifying design paths that do not meet required timing constraints. Design engineers are often forced to look at several different reports to obtain information about the required margin of setup, hold and pulse width relationships, and to determine additional information about the type of a delay relationship.
In order to improve the usability of STA results, timing diagrams have been generated from the STA database/reports via a graphical user interface (GUI) in order to graphically convey various timing relationships that may be of interest to the designer.
FIG. 1
illustrates an example of how a setup timing relationship between two signals is graphically represented in a conventional GUI environment. In the illustrated example, a first signal (“DATA”, in this example) is required to be valid (i.e., “stable”) at a latch for some period of time before a second signal (“CLK”, in this example) latches it.
While the graphical representation described above clearly coveys the setup time for the relationship between two signals, it does not convey the required timing margin, or the amount by which the signals either satisfy or violate the timing margin (i.e., the “slack time”).
Conventional STA graphical user interfaces may also enable the representation of delay relationships that are commonly drawn in typical timing diagrams.
FIG. 2A
illustrates a simple “AND” type logic gate as part of a larger logic system.
FIG. 2B
is a graphical illustration of the delay relationships present as a signal passes from the output of a first stage of the logic system to the inputs of the “AND” gate (the wire delay from “A” to “B”), through the “AND” gate (the gate delay from “B” to “C”), and from the output of the “AND” gate back into a second stage of the logic system (the wire delay from “C” to “D”).
While current drawing methods for delay relationships (i.e., such as those shown in
FIG. 2B
) show clearly that there is a delay between one signal and another signal, they do not convey information about the “type” or “kind” of delay (i.e., the delay from A to B and C to D are “wire” delays, and the delay from B to C is a block type of delay). Present systems also do not display the “characteristics” of the delay (e.g., the margin by which a signal meets or fails to meet a setup/hold timing requirement).
Thus, it is advantageous to improve existing timing diagrams generated to graphically display, by way of appropriate notations and symbols, additional information on the type and characteristics of various delay relationships.
SUMMARY OF THE INVENTION
The present invention provides a method and computer program product which graphically represents various types of timing relationships between signals in an electronic system. A timing analysis is performed on the electronic system, creating a set of timing results. The set of timing results is searched, and a set of timing waveforms meeting the search criteria is displayed. The type and characteristics of the timing relationship between the displayed waveforms is determined, and a graphical symbol representative of the type and characteristics of timing relationship is generated and added to the set of timing waveforms being displayed.
In an exemplary embodiment of the present invention, the timing analysis is a static timing analysis (STA). The present invention accommodates various types of timing relationships, including but not limited to: setup, hold, block delays, inverting delays, non-inverting delays, combinational logic delays, wire delays, rise triggered delays, and fall triggered delays. In one embodiment, the graphical symbols for the setup and hold type relationships include a graphical indication of timing characteristics for the relationships (e.g., the amount of time by which a signal either satisfies or violates the setup/hold time requirement). The present invention also provides an expand/collapse feature which enables a design engineer to select two or more signals on the display to “collapse” into a combinational logic delay symbol. In a similar manner, the design engineer may “expand” the combinational logic delay symbol back into the two or more signals.
These and other advantages and features, which characterize the invention, are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained though its use, reference should be made to the drawings, and to the accompanying descriptive matter, in which there is described exemplary embodiment of the invention.


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