SEU resistant SRAM using feedback MOSFET

Details SEU resistant SRAM using feedback MOSFET SEU resistant SRAM using feedback MOSFET

2002-04-04

2004-08-10

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S185070, C365S205000, C365S156000, C365S190000

Reexamination Certificate

active

06775178

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to SRAM memory cells which are resistant to a single event upset (SEU).
BACKGROUND OF THE INVENTION AND PRIOR ART
A memory, such as a static random access memory (SRAM), typically comprises a plurality of memory cells each of which stores a bit of information. A memory cell
10
that is popularly used in an SRAM is shown in FIG.
1
. The memory cell
10
is a six transistor cell and includes a first inverter
12
and a second inverter
14
. The first inverter
12
includes MOSFETs
16
and
18
, and the second inverter
14
includes MOSFETs
20
and
22
.
The source terminals of the MOSFETs
16
and
20
are coupled to a source VSS, and the drain terminals of the MOSFETs
18
and
22
are coupled to a reference VDD. The first and second inverters
12
and
14
are cross coupled. Accordingly, the gate terminals of the MOSFETs
16
and
18
are coupled to the drain terminal of the MOSFET
20
and to the source terminal of the MOSFET
22
, and the gate terminals of the MOSFETs
20
and
22
are coupled to the drain terminal of the MOSFET
16
and to the source terminal of the MOSFET
18
.
A first transmission gate
24
includes a MOSFET having its source/drain circuit coupled to the gate terminals of the MOSFETs
16
and
18
and its gate terminal coupled to a word line WL. Also, a second transmission gate
26
includes a MOSFET having its source/drain circuit coupled to the gate terminals of the MOSFETs
20
and
22
and its gate terminal coupled to the word line WL.
The memory cell
10
is vulnerable to high-energy particles from a radiation harsh environment and hence is prone to losing its programming state upon the occurrences of SEUs over a large range of incident radiation energy and/or charge.
A polysilicon resistor in the inverter cross coupling of the memory cell has been suggested as a solution to this loss of programming state upon the occurrence of a SEU. A memory cell
30
having such a resistor is shown in FIG.
2
. The memory cell
30
again is a six transistor cell and includes a first inverter
32
and a second inverter
34
. The first inverter
32
includes MOSFETs
36
and
38
, and the second inverter
34
includes MOSFETs
40
and
42
.
The source terminals of the MOSFETs
36
and
40
are coupled to a source VSS, and the drain terminals of the MOSFETs
38
and
42
are coupled to a reference VDD. The first and second inverters
32
and
34
are cross coupled. Accordingly, the gate terminals of the MOSFETs
36
and
38
are coupled to the drain terminal of the MOSFET
40
and to the source terminal of the MOSFET
42
through a feedback resistor
44
, and the gate terminals of the MOSFETs
40
and
42
are coupled directly to the drain terminal of the MOSFET
36
and to the source terminal of the MOSFET
38
.
A first transmission gate
46
includes a MOSFET having its source/drain circuit coupled to the gate terminals of the MOSFETs
36
and
38
and its gate terminal coupled to a word line WL. Also, a second transmission gate
48
includes a MOSFET having its source/drain circuit coupled to the gate terminals of the MOSFETs
40
and
42
and its gate terminal coupled to the word line WL.
Unfortunately, the resistance of the feedback resistor
44
changes exponentially with temperature. Hence, at high temperatures (minimum resistivity), the immunity provided by the memory cell
30
to SEUs is low. At low temperatures, the resistivity is high so that the immunity provided by the memory cell
30
to SEU events is also high. However, the high resistance at low temperatures degrades the programming speed of the memory cell
30
. Also, the polysilicon that is required to provide sufficient resistance for the feedback resistor
44
uses up too much valuable silicon.
Thus, two back-to-back Schottky diodes coupled in parallel to a seventh transistor has been suggested as an alternative solution to the problem of loss of programming state upon the occurrence of a SEU. A memory cell
50
of this type is shown in FIG.
3
. The memory cell
50
is a seven transistor plus Schottky diode cell and includes a first inverter
52
and a second inverter
54
. The first inverter
52
includes MOSFETs
56
and
58
, and the second inverter
54
includes MOSFETs
60
and
62
.
The source terminals of the MOSFETs
56
and
60
are coupled to a source VSS, and the drain terminals of the MOSFETs
58
and
62
are coupled to a reference VDD. The first and second inverters
52
and
54
are cross coupled. Accordingly, the gate terminals of the MOSFETs
56
and
58
are coupled to the drain terminal of the MOSFET
60
and to the source terminal of the MOSFET
62
through the source/drain circuit of a MOSFET
64
and parallel back-to-back Schottky diodes
66
, and the gate terminals of the MOSFETs
60
and
62
are coupled directly to the drain terminal of the MOSFET
56
and to the source terminal of the MOSFET
58
. The gate terminal of the MOSFET
64
is coupled to a word line WL.
A first transmission gate
68
includes a MOSFET having its source/drain circuit coupled to the gate terminals of the MOSFETs
56
and
58
and its gate terminal coupled to the word line WL. Also, a second transmission gate
70
includes a MOSFET having its source/drain circuit coupled to the gate terminals of the MOSFETs
60
and
62
and its gate terminal coupled to the word line WL.
The back-to-back Schottky diodes
66
provide the feedback resistance needed to resist SEUs. The MOSFET
64
is used only to provide a high conductivity path during write operations but has no use during the standby/programming state.
Unfortunately, control over the manufacturing of the Schottky diodes
66
during fabrication of the memory cell
50
is very poor due to processing complexity. This poor manufacturing control results in a wide variation in feedback resistance and, hence, a wide variation in SEU immunity. Also, for the memory cell
50
to operate properly during normal conditions, the feedback resistance value should be low enough to offer enough conductivity to keep the first and second inverters
52
and
54
cross coupled. The Schottky diodes
66
, due to the aforementioned poor manufacturing controls, often have a feedback resistance that is high enough to de-couple the first and second inverters
52
and
54
, which results in floating nodes. This floating node problem is even more severe at lower temperatures (such as −55 C) and results in unacceptable standby currents.
The present inventions solves one or more of these and/or other problems.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a random access memory cell comprises first and second inverters each having an input and an output. The input of the first inverter is coupled to the output of the second inverter by only one device having a junction, and the device comprises a MOSFET. The input of the second inverter is coupled to the output of the first inverter.
In accordance with another aspect of the present invention, a random access memory cell comprises first and second inverters and first and second transmission gates. The first inverter has an input and an output, and the second inverter has an input and an output. The first transmission gate is coupled to the input of the first inverter. The second transmission gate is coupled to the input of the second inverter. The input of the first inverter is coupled to the output of the second inverter by only one active device, and the device comprises a MOSFET. The input of the second inverter is coupled to the output of the first inverter.
In accordance with still another aspect of the present invention, a random access memory cell comprises first, second, third, fourth, fifth, and sixth MOSFETs, and a seventh Schottky-diode-free MOSFET each having a gate, a source, and a drain. The gates of the third and fourth MOSFETs are coupled together, and the gates of the fifth and sixth MOSFETs are coupled together. The sources of the third and fifth MOSFETs are coupled together, and the drains of the fourth a

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