SEU hardened latches and memory cells using programmable...

Details SEU hardened latches and memory cells using programmable... SEU hardened latches and memory cells using programmable...

2006-11-02

2010-06-29

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Systems using particular element

Resistive

C365S154000

Reexamination Certificate

active

07746682

ABSTRACT:
Apparatus and methods for reducing single-event upsets (SEUs) in latch-based circuitry (e.g., static random access memory (SRAM) cells) and other digital circuitry. According to an exemplary embodiment, a latch-based circuit includes a radiation-hardened latch having first and second cross-coupled inverters and first and second programmable resistance devices (PRDs). The first PRD is coupled between the output of the first inverter and the input of the second inverter. The second PRD is coupled between the output of the second inverter and the input of the first inverter. The PRDs may be programmed to low or high-resistance states. When SET to a low-resistance state, the latch of the latch-based circuitry may be accessed to read the current logic state stored by the latch or to write a new logic state into the latch. When RESET to a high-resistance state, the latch is in a radiation-hard state, thereby preventing the latch from generating SEUs.

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