SEU and SEFI fault tolerant computer

Details SEU and SEFI fault tolerant computer SEU and SEFI fault tolerant computer

2007-08-21

2007-08-21

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S017000, C714S822000

Reexamination Certificate

active

10767477

ABSTRACT:
A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run additional processors. Additionally, a hardened SEFI circuit is provided to periodically send a signal to the process which, in the case of a processor not in the SEFI state, initiates production by the processor of a “correct” response. If the correct response is not received within a particular time window, the SEFI circuit initiates progressively severe actions until a reset is achieved.

REFERENCES:
patent: 4132975 (1979-01-01), Koike
patent: 4199812 (1980-04-01), Klotzner et al.
patent: 4670880 (1987-06-01), Jitsukawa et al.
patent: 4817094 (1989-03-01), Lebizay et al.
patent: 4943969 (1990-07-01), Criswell
patent: 4959836 (1990-09-01), Berard et al.
patent: 5235220 (1993-08-01), Takizawa
patent: 5706423 (1998-01-01), Sugimoto
patent: 5822515 (1998-10-01), Baylocq
patent: 5903717 (1999-05-01), Wardrop
patent: 6298289 (2001-10-01), Lloyd et al.
patent: 6625756 (2003-09-01), Grochowski et al.
patent: 6910178 (2005-06-01), Kiselev et al.
patent: 7107515 (2006-09-01), Majumdar
patent: 2004/0153747 (2004-08-01), Czajkowski
patent: 2005/0055607 (2005-03-01), Czajkowski et al.
patent: 2 903 614 (1982-09-01), None
Mukherjee eta l.; “Detailed Design and Evaluation of Redundant Multithreading Alternatives”; International Conference on Computer Architecture, Proceedings of the 29thAnnual International Symposium on Computer Architecture; published 2002; pp. 99-110.
Reinhardt et al.; “Transient Fault Detection Via Simultaneious Multithreading”; International Conference on Computer Architecture, Proceedings of the 27thAnnual International Symposium on Computer Architecture; published 2000; pp. 25-36.
Oh et al.; “Error Detection by Duplicated Instructions in Super-Scalar Processors”; IEEE Transactions on Reliability, vol. 51, No. 1, Mar. 2002; pp. 63-75.

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