Setting fail bit verification circuit with different...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185220, C365S185290

Reexamination Certificate

active

07551479

ABSTRACT:
A reference fail bit verification circuit includes a fail bit counter which counts a number of fail bits to generate a first counting signal and a second counting signal, the first counting signal and the second counting signal being activated in response to the number of fail bits counted. The circuit also includes a bit verification block which generates a reference bit verification signal that is activated in response to a transition of the first counting signal and the second counting signal, wherein the reference bit verification signal is activated in response to at least one of the activation of the first counting signal in a first mode, and the activation of the second counting signal in a second mode.

REFERENCES:
patent: 5954828 (1999-09-01), Lin
patent: 7230852 (2007-06-01), Mitani et al.
patent: 1020000047814 (2000-07-01), None
patent: 1020000060206 (2000-10-01), None
patent: 1020010011482 (2001-02-01), None
patent: 1020020032171 (2002-05-01), None
patent: 1020020043378 (2002-06-01), None
patent: 1020030071630 (2003-09-01), None
patent: 100445794 (2004-08-01), None

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