Set/reset latch with minimum single event upset

Details Set/reset latch with minimum single event upset Set/reset latch with minimum single event upset

2008-01-10

2009-02-03

Lam, Tuan T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S202000, C327S203000

Reexamination Certificate

active

07486123

ABSTRACT:
A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes an L1latch and an L2latch coupled to the L1latch. Data is first latched in the L1latch during a first half clock cycle and then latched in the L2latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1latch and the L2latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

REFERENCES:
patent: 5001361 (1991-03-01), Tamamura et al.
patent: 6008678 (1999-12-01), Barber
patent: 6373771 (2002-04-01), Fifield et al.
patent: 6433586 (2002-08-01), Ooishi
patent: 6624677 (2003-09-01), Wissel

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